DAC5652A - Dual-Channel, 10-Bit, 275-MSPS Digital-to-Analog Converter (DAC)

Updated : 2020-01-09 14:29:45
Description

The DAC5652A is a monolithic, dual-channel, 10-bit, high-speed digital-to-analogconverter (DAC) with on-chip voltage reference.

Operating with update rates of up to 275 MSPS, the DAC5652A offers exceptional dynamicperformance, tight-gain, and offset matching characteristics that make it suitable in either I/Qbaseband or direct IF communication applications.

Each DAC has a high-impedance, differential-current output, suitable for single-ended ordifferential analog-output configurations. External resistors allow scaling of the full-scaleoutput current for each DAC separately or together, typically between 2 mA and 20 mA. An accurateon-chip voltage reference is temperature-compensated and delivers a stable 1.2-V reference voltage.Optionally, an external reference may be used.

The DAC5652A has two, 10-bit, parallel input ports with separate clocks and data latches.For flexibility, the DAC5652A also supports multiplexed data for each DAC on one port whenoperating in the interleaved mode.

The DAC5652A has been specifically designed for a differential transformer-coupled outputwith a 50-Ω doubly-terminated load. For a 20-mA full-scale output current, both a 4:1 impedanceratio (resulting in an output power of 4 dBm) and 1:1 impedance ratio transformer (–2-dBm outputpower) are supported.

The DAC5652A is available in 48-pin TQFP and 48-pin VQFN packages. The TQFP packageoffers pin compatibility between family members that provides 10-bit (DAC5652A), 12-bit (DAC5662),and 14-bit (DAC5672) resolution. The TQFPpackage is also pin compatible to the DAC2900 andAD9763 dual DACs. The device is characterizedfor operation over the industrial temperature range of –40°C to +85°C.

Products containing the "DAC5652A" keyword are: DAC5652AEVM , DAC5652AI , DAC5652AIPFB , DAC5652AIPFB , DAC5652AIPFBG4 , DAC5652AIPFBR , DAC5652AIPFBRG4 , DAC5652AIRSLR , DAC5652AIRSLT
Features

  • 10-Bit Dual Transmit DAC
  • 275 MSPS Update Rate
  • Single Supply: 3.0 V to 3.6 V
  • High Spurious-Free Dynamic Range (SFDR): 80 dBc at 5 MHz
  • High Third-Order Two-Tone Intermodulation (IMD3): 78 dBc at 15.1 MHz and 16.1 MHz
  • Independent or Single Resistor Gain Control
  • Dual or Interleaved Data
  • On-Chip 1.2-V Reference
  • Low Power: 290 mW
  • Power-Down Mode: 9 mW
  • Packages:
    • 48-Pin Thin-Quad Flat Pack (TQFP)
    • 48-Pin Very-Thin-Quad Flat No-Leads (VQFN)

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Parametrics
StatusACTIVE
SubFamilyHigh-speed DACs (>10MSPS)
Resolution10
Settling Time0.02
Sample / Update Rate275
DAC channels2
ArchitectureCurrent Source
Power consumption290
InterfaceParallel CMOS
INL
Reference: typeExt^Int
Output type
RatingCatalog
Operating temperature range-40 to 85
Package GroupTQFP|48
Package size: mm2:W x L (PKG)[pf]48TQFP[/pf]: 81 mm2: 9 x 9 (TQFP|48)
Approx. price8.15 | 1ku
SFDR80