ADS61JB23 - 12-Bit, 80-MSPS Analog-to-Digital Converter (ADC)

The ADS61JB23 is a high-performance, low-power, single channel analog-to-digital converter with an integrated JESD204A output interface. Available in a 6 mm × 6 mm QFN package, with both single-lane and dual-lane output modes, the ADS61JB23 offers an unprecedented level of compactness. The output interface is compatible to the JESD204A standard, with an additional mode (as per IEEE Std 802.3-2002 part3, Clause 36.2.4.12) to interface seamlessly to the TI TLK family of SERDES transceivers. Equally impressive is the inclusion of an on-chip analog input buffer, providing isolation between the sample/hold switches and higher and more consistent input impedance.

The ADS61JB23 is specified over the industrial temperature range (–40°C to 85°C).

• Output Interface:
  • Single-Lane and Dual-Lane Interfaces
  • Maximum Data Rate of 1.6 Gbps
  • Meets JESD204A Specification
  • CML Outputs with Current Programmable from 2 mA – 32 mA
• Power Dissipation:
  • 440 mW at 80 MSPS in Single Lane Mode
  • Power Scales Down with Clock Rate
• Input Interface: Buffered Analog Inputs
• 71.7 dBFS SNR at 70 MHz IF
• Analog Input FSR: 2 Vpp
• External and Internal (trimmed) Reference Support
• 1.8V Supply (Analog and digital), 3.3 V Supply for Input Buffer
• Programmable Digital Gain: 0dB – 6dB
• Straight Offset Binary or Twos Complement Output
• Package:
  • 6 mm × 6 mm QFN-40