ADS5296A - 10-Bit, 200-MSPS, 4 or 8-Channel / 12-Bit, 80-MSPS, 8-Channel ADC

The ADS5296A is a low-power, 12-bit, 8-channel, analog-to-digital converter (ADC) with sample rates up to 80 MSPS. However, the device can also be configured to operate as a 4-channel ADC running at 2x the sample rate by interleaving data from two ADC channels. In interleaving mode, the device accepts a double frequency input clock. Each ADC in a pair converts a common analog input signal at alternate rising edges of the 2x input clock. The device can either be configured as a 10-bit, 4-channel ADC with sample rates up to 200 MSPS or as a 12-bit, 4-channel ADC with sample rates up to 160 MSPS.

The data from each ADC within the interleaved pair is output in serial format over one LVDS pair up to a maximum data rate of 1 Gbps (10 bits at 100 MSPS). With interleaving disabled, the ADS5296A can also be operated as an 8-channel, 10-bit device with sample rates up to 100 MSPS.

Several digital functions commonly used in systems are included in the device. These functions include a low-frequency noise suppression (LFNS) mode, digital filtering options, and programmable mapping of LVDS output pins and analog input channels.

For low input frequency applications, the LFNS mode enables the suppression of noise at low frequencies and improves SNR in the 1-MHz band near dc by approximately 3 dB. Digital filtering options include low-pass, high-pass, and band-pass digital filters as well as dc offset removal filters.

Low power consumption and integration of multiple channels in a small package makes the device attractive for high channel count data acquisition systems. The device is available in a compact 9-mm × 9-mm QFN-64 package. The ADS5296A is specified over the –40°C to +85°C operating temperature range.

• Configurable Modes of Operation:
  • 10-Bit, 200-MSPS, 4-Channel ADC
  • 12-Bit, 160-MSPS, 4-Channel ADC
  • 10-Bit, 100-MSPS, 8-Channel ADC
  • 12-Bit, 80-MSPS, 8-Channel ADC
• Designed for Low Power:
  • 65 mW per Channel at 80 MSPS
    (12-Bit, 8-Channel)
  • 150 mW per Channel at 200 MSPS
    (10-Bit, 4-Channel)
• 12-Bit, 80 MSPS:
  • SNR: 70.3 dBFS
• 10-Bit, 200 MSPS:
  • SNR: 61.3 dBFS
  • Interleaving Spur: > 60 dBc at 90 MHz
• Serial LVDS One-Wire Interface:
  • 10x Serialization up to 1000 Mbps Data Rate per Wire
  • 12x Serialization up to 960 Mbps Data Rate per Wire
• Digital Processing Block:
  • Programmable FIR Decimation Filter and Oversampling to Minimize Harmonic Interference
  • Programmable IIR High-Pass Filter to Minimize DC Offset
  • Programmable Digital Gain: 0 dB to 12 dB
• Low-Frequency Noise Suppression Mode
• Programmable Mapping Between ADC Input Channels and LVDS Output Pins
• Channel Averaging Mode
• Variety of LVDS Test Patterns to Verify
  Data Capture by FPGA or Receiver
• Package: 9-mm × 9-mm QFN-64