The ADC12DC105 is a high-performance CMOS analog-to-digital converter capable of converting two analog input signals into 12-bit digital words at rates up to 105 Mega Samples Per Second (MSPS). These converters use a differential, pipelined architecture with digital error correction and an on-chip sample-and-hold circuit to minimize power consumption and the external component count, while providing excellent dynamic performance. A unique sample-and-hold stage yields a full-power bandwidth of 1 GHz. The ADC12DC080/105 may be operated from a single +3.0V or +3.3V power supply. A power-down feature reduces the power consumption to very low levels while still allowing fast wake-up time to full operation. The differential inputs provide a 2V full scale differential input swing. A stable 1.2V internal voltage reference is provided, or the ADC12DC105 can be operated with an external 1.2V reference. Output data format (offset binary versus 2's complement) and duty cycle stabilizer are pin-selectable. The duty cycle stabilizer maintains performance over a wide range of clock duty cycles.
The ADC12DC105 is available in a 60-lead WQFN package and operates over the industrial temperature range of −40°C to +85°C.
Products containing the "ADC12DC105" keyword are: ADC12DC105CISQ , ADC12DC105CISQ/NOPB , ADC12DC105CISQ/NOPB , ADC12DC105CISQE , ADC12DC105CISQE/NOPB , ADC12DC105CISQE/NOPB , ADC12DC105LFEB/NOPB , ADC12DC105LFEB/NOPBAll trademarks are the property of their respective owners.
| Status | ACTIVE |
| SubFamily | High-speed ADCs (>10MSPS) |
| Resolution | 12 |
| Sample Rate | 105 |
| Number of input channels | 2 |
| INL | |
| SNR | 69.1 |
| SFDR | 83 |
| Power consumption | 800 |
| Interface | Parallel CMOS |
| Architecture | Pipeline |
| Operating temperature range | -45 to 85 |
| Rating | Catalog |
| Package Group | WQFN|60 |
| Package size: mm2:W x L (PKG) | [pf]60WQFN[/pf]: 81 mm2: 9 x 9 (WQFN|60) |
| Approx. price | 34.30 | 1ku |
| Analog input BW | 1000 |