The ADC14155QML-SP is a high-performance CMOS analog-to-digital converter capable ofconverting analog input signals into 14-bit digital words at rates up to 155 MSPS. This converteruses a differential, pipelined architecture with digital error correction and an on-chipsample-and-hold circuit to minimize power consumption and the external component count, whileproviding excellent dynamic performance. A unique sample-and-hold stage yields a full-powerbandwidth of 1.1 GHz. The ADC14155 operates from dual 3.3-V and 1.8-V power supplies and consumes967 mW of power at 155 MSPS.
The separate 1.8-V supply for the digital output interface allows lower power operationwith reduced noise. A power-down feature reduces the power consumption to 5 mW with the clock inputdisabled, while still allowing fast wake-up time to full operation. The differential inputs providea full scale differential input swing equal to 2 times the reference voltage. A stable 1-V internalvoltage reference is provided, or the ADC14155 can be operated with an external reference. TheClock mode (differential versus single-ended) and output data format (offset binary versus 2scomplement) are pin-selectable. A duty cycle stabilizer maintains performance over a wide range ofclock duty cycles.
The ADC14155QML-SP is available in a 48-lead thermally enhanced multi-layer ceramic quadpackage and operates over the military temperature range of –55°C to +125°C.
Products containing the "ADC14155QML-SP" keyword are: ADC14155QML-SPAll trademarks are the property of their respective owners.
Status | ACTIVE |
SubFamily | High-speed ADCs (>10MSPS) |
Resolution | 14 |
Sample Rate | 155 |
Number of input channels | 1 |
INL | |
SNR | 71.3 |
SFDR | 87 |
Power consumption | 967 |
Interface | Parallel CMOS |
Architecture | Pipeline |
Operating temperature range | -55 to 125 |
Rating | Space |
Package Group | CFP|48 |
Package size: mm2:W x L (PKG) | See datasheet (CFP) |
Approx. price | |
Analog input BW | 1100 |