ADC14155 - 14-Bit, 155-MSPS, 1.1-GHz Input Bandwidth Analog-to-Digital Converter (ADC)

The ADC14155 is a high-performance CMOS analog-to-digital converter capable of converting analog input signals into 14-bit digital words at rates up to 155 Mega Samples Per Second (MSPS). This converter uses a differential, pipelined architecture with digital error correction and an on-chip sample-and-hold circuit to minimize power consumption and the external component count, while providing excellent dynamic performance. A unique sample-and-hold stage yields a full-power bandwidth of 1.1 GHz. The ADC14155 operates from dual +3.3V and +1.8V power supplies and consumes 967 mW of power at 155 MSPS.

The separate +1.8V supply for the digital output interface allows lower power operation with reduced noise. A power-down feature reduces the power consumption to 5 mW with the clock input disabled, while still allowing fast wake-up time to full operation.

The differential inputs provide a full scale differential input swing equal to 2 times the reference voltage. A stable 1.0V internal voltage reference is provided, or the ADC14155 can be operated with an external reference.

The ADC14155 can be configured for either single-ended or differential operation. Clock mode (differential versus single-ended) and output data format (offset binary versus 2's complement) are pin-selectable. A duty cycle stabilizer maintains performance over a wide range of clock duty cycles.

The ADC14155 is available in a 48-lead WQFN package and operates over the industrial temperature range of −40°C to +85°C.

Products containing the "ADC14155" keyword are: ADC14155CISQ , ADC14155CISQ/NOPB , ADC14155CISQ/NOPB , ADC14155HCVAL , ADC14155HFEB , ADC14155HFEB/NOPB , ADC14155HFEB/NOPB , ADC14155LFEB , ADC14155LFEB/NOPB , ADC14155LFEB/NOPB , ADC14155QML-SP , ADC14155W-MLS , ADC14155W-MLS 155 MS

• 1.1 GHz Full Power Bandwidth
• Internal Sample-and-Hold Circuit
• Low Power Consumption
• Internal Precision 1.0V Reference
• Single-Ended or Differential Clock Modes
• Data Ready Output Clock
• Clock Duty Cycle Stabilizer
• Dual +3.3V and +1.8V Supply Operation
  (+/- 10%)
• Power-Down Mode
• Offset Binary or 2's Complement Output Data Format
• 48-pin WQFN Package, (7x7x0.8mm, 0.5mm Pin-Pitch)

Key Specifications

• Resolution: 14 Bits
• Conversion Rate: 155 MSPS
• SNR (f_IN = 70 MHz): 71.3 dBFS (typ)
• SFDR (f_IN = 70 MHz): 87.0 dBFS (typ)
• ENOB (f_IN = 70 MHz): 11.5 bits (typ)
• Full Power Bandwidth: 1.1 GHz (typ)
• Power Consumption: 967 mW (typ)

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