These devices are precision timing circuits capable of producing accurate time delays or oscillation. In the time-delay or mono-stable mode of operation, the timed interval is controlled by a single external resistor and capacitor network. In the a-stable mode of operation, the frequency and duty cycle can be controlled independently with two external resistors and a single external capacitor.
The threshold and trigger levels normally are two-thirds and one-third, respectively, of VCC. These levels can be altered by use of the control-voltage terminal. When the trigger input falls below the trigger level, the flip-flop is set, and the output goes high. If the trigger input is above the trigger level and the threshold input is above the threshold level, the flip-flop is reset and the output is low. The reset (RESET) input can override all other inputs and can be used to initiate a new timing cycle. When RESET goes low, the flip-flop is reset, and the output goes low. When the output is low, a low-impedance path is provided between discharge (DISCH) and ground.
The output circuit is capable of sinking or sourcing current up to 200 mA. Operation is specified for supplies of 5 V to 15 V. With a 5-V supply, output levels are compatible with TTL inputs.
Products containing the "SE555" keyword are: SE555 , SE555BJG , SE555CH , SE555CJB , SE555CN , SE555D , SE555D , SE555DF , SE555DG4 , SE555DG4 , SE555DR , SE555DR , SE555DR G4 , SE555DRE4 , SE555DRG4 , SE555DRG4 , SE555DT , SE555FE , SE555FKB , SE555HStatus | ACTIVE |
SubFamily | Timers |
Frequency | 0.1 |
VCC | 18 |
Iq | 4000 |
Rating | Catalog |
Operating temperature range | -55 to 125 |
Package Group | PDIP|8 |
Package size: mm2:W x L (PKG) | See datasheet (PDIP) |
Approx. price | 0.09 | 1ku |