AFE58JD28 - 16-Ch Ultrasound AFE With 102mW/Ch Power, Digital Demodulator, and JESD or LVDS Interface

The AFE58JD28 device is a highly-integrated, analog front-end (AFE)solutions specifically designed for ultrasound systems where high performance, low power, and smallsize are required.

The AFE58JD28 is an integrated AFE optimized for medical ultrasoundapplication. The device is realized through a multichip module (MCM) with two dies: onevoltage-controlled amplifier (VCA) die and one analog-to-digital converter (ADC) die. The VCA diehas 16 channels that interface with the 16 channels of the ADC die.

Each channel in the VCA die can be configured in one of two modes: time gain compensation(TGC) mode or continuous wave (CW) mode. In TGC mode, each channel includes a low-noise amplifier(LNA), a voltage-controlled attenuator (VCAT), a programmable gain amplifier (PGA), and athird-order, low-pass filter (LPF). The LNA is programmable in gains of 21 dB, 18 dB, or 15 dB. TheLNA also supports active termination. The VCAT supports an attenuation range of 0 dB to 36 dB, withanalog voltage control for the attenuation. The PGA provides gain options from 18 dB to 27 dB insteps of 3 dB. The LPF cutoff frequency can be set between 10 MHz and 30 MHz tosupport ultrasound applications with different frequencies. In CW mode, the output of the LNA goesto a low-power passive mixer with 16 selectable phase delays followed by a summing amplifier with aband-pass filter. Different phase delays can be applied to each analog input signal to perform anon-chip beamforming operation. A harmonic filter in the CW mixer suppresses the third and fifthharmonic to enhance the sensitivity of the CW Doppler measurement.

The 16 channels of the ADC die can be configured to operate with a resolution of 14 bitsor 12 bits. The ADC resolution can be traded off with conversion rate, and can operate at maximumspeeds of 65 MSPS and 80 MSPS at 14-bit and 12-bit resolution, respectively. The ADCis designed to scale its power with sampling rate. The output interface of the ADC comes outthrough a low-voltage differential signaling (LVDS) that can easily interface with low-costfield-programmable gate arrays (FPGAs).

The AFE58JD28 additionally includes a digitaldemodulator and JESD204B data packing blocks. The digital in-phase and quadrature (I/Q) demodulatorwith programmable decimation filters accelerates computationally-intensive algorithms at low power.The device also supports an optional JESD204B interface that runs up to 5 Gbps andfurther reduces the circuit-board routing challenges in high-channel count systems.

The device also allows various power and noise combinations to be selected for optimizingsystem performance. Therefore, these devices are suitable ultrasound AFE solutions for systems withstrict battery-life requirements.

The device is available in a 15-mm × 15-mm NFBGA-289 package and is pin-compatible withthe AFE5818 andAFE5816 family.

• 16-Channel AFE for Ultrasound Applications:
  • Optimized Signal Chains for TGC and CW Modes
  • Four Programmable TGC Profiles
• Low-Noise Amplifier (LNA) With:
  • Programmable Gain: 21 dB, 18 dB, and 15 dB
  • Linear Input Signal Amplitude:
    0.37 V_PP, 0.5 V_PP, and 0.71 V_PP
  • Active Termination
• Voltage-Controlled Attenuator (VCAT):
  • Attenuation Range: 0 dB–36 dB
• Programmable Gain Amplifier (PGA):
  • 18 dB–27 dB in Steps of 3 dB
• 3rd-Order, Linear-Phase, Low-Pass Filter (LPF):
  • Cutoff Frequency From 10 MHz to 30 MHz
• ADC Modes (Idle-Channel SNR):
  • 14-Bit, 65-MSPS Mode: 75-dBFS
  • 12-Bit, 80-MSPS Mode: 72-dBFS
• Optimized for Noise and Power:
  • TGC Mode: 102 mW/Ch at 0.8 nV/√Hz,
    65-MSPS, 14-Bit Output
  • CW Mode: 63 mW/Ch
• Excellent Device-to-Device Gain Matching:
  • ±0.4 dB (Typical)
• Fast and Consistent Overload Recovery
• Continuous Wave (CW) Path With:
  • Low Close-In Phase Noise of –159 dBc/Hz at 1-kHz Frequency Offset off 2.5-MHz Carrier
  • Phase Resolution: λ / 16
  • Supports 16x and 8x CW Clocks
  • 12-dB Suppression of 3rd and 5th Harmonics
• Digital I/Q Demodulator:
  • Fractional Decimation Filter M = 1 to 63 With Increments of 0.25
  • Data Throughput Reduction After Decimation
  • On-Chip RAM With 32 Preset Profiles
• LVDS Interface With a Speed Up to 1 Gbps
• 5-Gbps JESD Interface:
  • JESD204B Subclass 0, 1, and 2
  • 2, 4, or 8 Channels per JESD Lane
• Small Package: 15-mm × 15-mm NFBGA-289

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