AFE58JD32 - 32-Ch Ultrasound AFE With 42mW/Ch Power, Digital Demodulator, and JESD204B and LVDS Interface

The AFE58JD32 device is a highly-integrated, analog front-end solutionspecifically designed for ultrasound systems where high performance, low power, and small size arerequired.

The AFE58JD32 is an integrated analog front-end (AFE) optimized formedical ultrasound application. The device is realized through a multichip module (MCM) with threedies: two voltage-controlled amplifier (VCA) dies and one analog-to-digital converter (ADC) die.Each VCA die has 16 channels and the ADC die converts all of the 32 channels.

Each channel in the VCA die is configured in either of two modes: time gain compensation(TGC) mode or continuous wave (CW) mode. In TGC mode, each channel includes an input attenuator(ATTEN), a low-noise amplifier (LNA) with variable-gain, and a third-order, low-pass filter (LPF).The attenuator supports an attenuation range of 8 dB to 0 dB, and the LNA supports gain ranges from20 dB to 51 dB. The LPF cutoff frequency can be configured at 5 MHz, 7.5 MHz, 10 MHz, or 12.5 MHzto support ultrasound applications with different frequencies. In CW mode, each channel includes anLNA with a fixed gain of 18 dB, and a low-power passive mixer with 16 selectable phase delays.Different phase delays can be applied to each analog input signal to perform an on-chip beamformingoperation. A harmonic filter in the CW mixer suppresses the third and fifth harmonic to enhance thesensitivity of the CW Doppler measurement.

The ADC die has 16 physical ADCs. Each ADC converts two sets of outputs – one from eachVCA die. The ADC is configured to operate with a resolution of 12 bits or 10 bits. The ADCresolution can be traded off with conversion rate, and operates at maximum speeds of 80 MSPS and100 MSPS at 12-bit and 10-bit resolution, respectively. The ADC is designed to scale its power withsampling rate. The output interface of the ADC comes out through a low-voltage differentialsignaling (LVDS) which can easily interface with low-cost field-programmable gate arrays(FPGAs).

The AFE58JD32 includes an optional digital demodulator andJESD204B data packing blocks. The digital in-phase and quadrature (I/Q) demodulator withprogrammable decimation filters accelerates computationally-intensive algorithms at low power. Thedevice also supports an optional JESD204B interface that runs up to 5-Gbps and further reduces thecircuit-board routing challenges in high-channel count systems.

The AFE58JD32 also allows various power and noise combinations to beselected for optimizing system performance. Therefore, this device is a suitable ultrasound AFEsolution for systems with strict battery-life requirements.

• 32-Channel, AFE for Ultrasound Applications:
  • Input Attenuator, LNA, LPF, ADC,
    Digital I/Q Demodulator and CW Mixer
  • Digital Time Gain Compensation (DTGC)
  • Total Gain Range: 12 dB to 51 dB
  • Linear Input Range: 800 mV_PP
• Input Attenuator With DTGC:
  • 8-dB to 0-dB Attenuation With 0.125-dB Step
  • Supports Matched Impedance for:
    • 50-Ω to 800-Ω Source Impedance
• Low-Noise Amplifier (LNA) With DTGC:
  • 20-dB to 51-dB Gain With 0.125-dB Step
  • Low Input Current Noise: 1.2 pA/√Hz
• 3rd-Order, Linear-Phase, Low-Pass Filter (LPF):
  • 5 MHz, 7.5 MHz, 10 MHz, and 12.5 MHz
• 16 ADCs Converting at 12-Bit, 80 MSPS or 10-bit, 100 MSPS:
  • Each ADC Converts Two Sets of Inputs at Half Rate
  • 12-Bit ADC: 72-dBFS SNR
  • 10-Bit ADC: 61-dBFS SNR
• Optimized for Noise and Power:
  • 35 mW/Ch at 2.1 nV/√Hz, 40 MSPS
  • 42 mW/Ch at 1.4 nV/√Hz, 40 MSPS
  • 52 mW/Ch at 1.3 nV/√Hz, 40 MSPS
  • 60 mW/Ch in CW Mode
• Excellent Device-to-Device Gain Matching:
  • ±0.5 dB (Typical)
• Low Harmonic Distortion: –55 dBc
• Fast and Consistent Overload Recovery
• Continuous Wave (CW) Path With:
  • Low Close-In Phase Noise of –151 dBc/Hz
    at 1-kHz Frequency Offset Off 2.5-MHz Carrier
  • Phase Resolution: λ / 16
  • Supports 16X CW Clock
  • 12-dB Suppression on Third and Fifth Harmonics
• Digital I/Q Demodulator After ADC:
  • Decimation Filter M = 1 to 63
  • Data Throughput Reduction After Decimation
  • On-Chip RAM with 32 Preset Profiles
• LVDS Interface With a Speed Up to 1 Gbps
• 5-Gbps JESD Interface:
  • JESD204B Subclass 0, 1, and 2
  • 2, 4, or 8 Channels per JESD Lane
• Small Package: 15-mm × 15-mm NFBGA-289

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