LMK04832 - Ultra Low-Noise JESD204B Compliant Clock Jitter Cleaner With Dual Loop

The LMK04832 is an ultra-high performance clock conditioner withJEDEC JESD204B support and is also pin compatible with the LMK0482x family of devices.

The 14 clock outputs from PLL2 can be configured to drive seven JESD204B converters orother logic devices using device and SYSREF clocks. SYSREF can be provided using both DC and ACcoupling. Not limited to JESD204B applications, each of the 14 outputs can be individuallyconfigured as high performance outputs for traditional clocking systems.

The LMK04832 can be configured for operation in dual PLL, single PLL, or clockdistribution modes with or without SYSREF generation or reclocking. PLL2 may operate with eitherinternal or external VCO.

The high performance combined with features like the ability to trade off between powerand performance, dual VCOs, dynamic digital delay, and holdover make the LMK04832 ideal forproviding flexible high performance clocking trees.

• Maximum Clock Output Frequency: 3255 MHz
• Multi-Mode: Dual PLL, Single PLL, and Clock Distribution
• Ultra-Low Noise, at 2500 MHz:
  • 54 fs RMS Jitter (12 kHz to 20 MHz)
  • 64 fs RMS Jitter (100 Hz to 20 MHz)
  • –157.6 dBc/Hz Noise Floor
• Ultra-Low Noise, at 3200 MHz:
  • 61 fs RMS Jitter (12 kHz to 20 MHz)
  • 67 fs RMS Jitter (100 Hz to 100 MHz)
  • –156.5 dBc/Hz Noise Floor
• PLL2
  • PLL FOM of –230 dBc/Hz
  • PLL 1/f of –128 dBc/Hz
  • Phase Detector Rate up to 320 MHz
  • Two Integrated VCOs: 2440 to 2580 MHz
    and 2945 to 3255 MHz
• Up to 14 Differential Device Clocks
  • CML, LVPECL, LCPECL, HSDS, LVDS, and 2xLVCMOS Programmable Outputs
• Up to 1 Buffered VCXO/XO Output
  • LVPECL, LVDS, 2xLVCMOS Programmable
• 1-1023 CLKout Divider
• 1-8191 SYSREF Divider
• 25-ps Step Analog Delay for SYSREF Clocks
• Digital Delay and Dynamic Digital Delay for Device Clock and SYSREF
• Holdover Mode With PLL1
• 0-Delay with PLL1 or PLL2
• Supports 105°C PCB Temperature
  (Measured at Thermal Pad)

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