LMK04610 - Ultra Low-Noise and Low Power JESD204B Compliant Clock Jitter Cleaner With Dual PLLs

The LMK0461x device family is the industry’s highestperformance and lowest power jitter cleaner with JESD204B support.

• Dual Loop PLL Architecture
  • 65-fs RMS Jitter (10 kHz to 20 MHz)
  • 85-fs RMS Jitter (100 Hz to 20 MHz)
  • –165-dBc/Hz Noise Floor at 122.88 MHz
• JESD204B Support
  • Single Shot, Pulsed, and Continuous SYSREF
• 10 Differential Output Clocks in 8 Frequency Groups
  • Programmable Output Swing Between 700 mVpp to 1600 mVpp
  • Each Output Pair Can be Configured to SYSREF Clock Output
  • 16-Bit Channel Divider
  • Minimum SYSREF Frequency of 25 kHz
  • Maximum Output Frequency of 2 GHz
  • Precision Digital Delay, Dynamically Adjustable
    • Digital Delay (DDLY) of ½ × Clock Distribution Path Frequency (2 GHz Maximum)
  • 60-ps Step Analog Delay
  • 50% Duty Cycle Output Divides, 1 to 65535
    (Even and Odd)
• 2 Reference Inputs
  • Holdover Mode, When Inputs are Lost
  • Automatic and Manual Switch-Over Modes
  • Loss-of-Signal (LOS) Detection
• 0.88-W Typical Power Consumption With 10 Outputs Active
• Operates Typically From a 1.8-V (Outputs, Inputs) and 3.3-V Supply (Digital, PLL1, PLL2_OSC, PLL2 Core)
• Fully Integrated Programmable Loop Filter
• PLL2
  • PLL2 Phase Detector Rate Up to 250 MHz
  • OSCin Frequency-Doubler
  • Integrated Low-Noise VCO
• Internal Power Conditioning: Better Than –80dBc PSRR on VDDO for 122.88-MHz Differential Outputs
• 3- or 4-Wire SPI Interface (4-Wire is Default)
• –40ºC to +85ºC Industrial Ambient Temperature
• Supports 105ºC PCB Temperature (Measured at Thermal Pad)
• LMK04610: 8-mm × 8-mm VQFN-56 Package With 0.5-mm Pitch

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