CD74HC93 - High Speed CMOS Logic 4-Bit Binary Ripple Counter

The CD74HC93 and CD74HCT93 are high-speed silicon-gate CMOS devices and are pin-compatible with low power Schottky TTL (LSTTL). These 4-bit binary ripple counters consist of four master-slave flip-flops internally connected to provide a divide-by-two section and a divide-by-eight section. Each section has a separate clock input (CP0\ and CP1\) to initiate state changes of the counter on the HIGH to LOW clock transition. State changes of the Q_n outputs do not occur simultaneously because of internal ripple delays. Therefore, decoded output signals are subject to decoding spikes and should not be used for clocks or strobes.

A gated AND asynchronous master reset (MR1 and MR2 is provided which overrides both clocks and resets (clears) all flip-flops.

Because the output from the divide by two section is not internally connected to the succeeding stages, the device may be operated in various counting modes.

In a 4-bit ripple counter the output Q₀ must be connected externally to input CP1\. The input count pulses are applied to clock input CP0\. Simultaneous frequency divisions of 2, 4, 8, and 16 are performed at the Q₀, Q₁, Q₂, and Q₃ outputs as shown in the function table. As a 3-bit ripple counter the input count pulses are applied to input CP1\.

Simultaneous frequency divisions of 2, 4, and 8 are available at the Q₁, Q₂, Q₃ outputs. Independent use of the first flip-flop is available if the reset function coincides with the reset of the 3-bit ripple-through counter.

Products containing the "CD74HC93" keyword are: CD74HC93E , CD74HC93E , CD74HC93EE4 , CD74HC93EE4 , CD74HC93EG4 , CD74HC93M , CD74HC93M , CD74HC93M96 , CD74HC93M96 , CD74HC93M96E4 , CD74HC93M96G4 , CD74HC93M96G4 , CD74HC93ME4 , CD74HC93MG4 , CD74HC93MT , CD74HC93MT , CD74HC93MTE4 , CD74HC93MTG4

• Can Be Configured to Divide By 2, 8, and 16
• Asynchronous Master Reset
• Fanout (Over Temperature Range)
  • Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads
  • Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
• Wide Operating Temperature Range . . . –55°C to 125°C
• Balanced Propagation Delay and Transition Times
• Significant Power Reduction Compared to LSTTL Logic ICs
• HC Types
  • 2V to 6V Operation
  • High Noise Immunity: N_IL = 30%, N_IH = 30% of V_CC at V_CC = 5V
• HCT Types
  • 4.5V to 5.5V Operation
  • Direct LSTTL Input Logic Compatibility, V_IL = 0.8V (Max), V_IH = 2V (Min)
  • CMOS Input Compatibility, I_l 1µA at V_OL , V_OH

Data sheet acquired from Harris Semiconductor