CD4018B - CMOS Presettable Divide-By-N Counter

CD4018B types consist of 5 Johnson-Counter stages, buffered Q outputs from each stage, and counter preset control gating. CLOCK, RESET, DATA, PRESET ENABLE, and 5 individual JAM inputs are provided. Divide by 10, 8, 6, 4, or 2 counter configurations can be implemented by feeding the Q\5, Q\4, Q\3, Q\2, Q\1 signals, respectively, back to the DATA input. Divide-by-9, 7, 5, or 3 counter configurations can be implemented by the use of a CD4011B to gate the feedback connection to the DATA input. Divide-by functions grater than 10 can be achieved by use of multiple CD4018B units. The counter is advanced one count at the positive clock-signal transition.. Schmitt Trigger action on the clock line permits unlimited clock rise and fall times. A high RESET signal clear the counter to an all-zero condition. A high PRESET-ENABLE signal allows information on the JAM inputs to preset the counter. Anti-lock gating is provided to assure the proper counting sequence.

The CD4018B types are supplied in 16-lead hermetic dual-in-line ceramic packages (F3A suffix), 16-lead dual-in-line plastic packages (E suffix), 16-lead small-outline packages (M, M96, MT, and NSR suffixes), and 16-lead thin shrink small-outline packages (PW and PWR suffixes).

Products containing the "CD4018B" keyword are: CD4018BCN , CD4018BD/3 , CD4018BDB , CD4018BE , CD4018BE , CD4018BEE4 , CD4018BEG4 , CD4018BF , CD4018BF/3 , CD4018BF3A , CD4018BFB , CD4018BFX , CD4018BM , CD4018BM , CD4018BM96 , CD4018BM96 , CD4018BM96E4 , CD4018BM96G4 , CD4018BME4 , CD4018BMG4

• Medium speed operation……10 MHz (typ.) at V_DD – V_SS = 10 V
• Fully static operation
• 100% tested for quiescent current at 20 V
• Standardized, symmetrical output characteristics
• 5-V, 10-V, and 15-V parametric ratings
• Maximum input current of 1 µA at 18 V over full package-temperature range; 100 nA at 18 V and 25°C
• Noise margin (full package-temperature range) =
          1 V at V_DD = 5 V
          2 V at V_DD = 10 V
       2.5 V at V_DD = 15 V
• Meets all requirements of JEDEC Tentative Standard No. 13B, "Standard Specifications for Description of ’B’ Series CMOS Devices"
• Applications:
  • Fixed and programmable divide-by-10, 9, 8, 7, 6, 5, 4, 3, 2 counters
  • Fixed and programmable counters greater than 10
  • Programmable decade counters
  • Divide-by-"N" counters/frequency synthesizers
  • Frequency division
  • Counter control/timers