CD4029B - CMOS Presettable Up/Down Counter

CD4029B consists of a four-stage binary or BCD-decade up/down counter with provisions for look-ahead carry in both counting modes. The inputs consist of a single CLOCK, CARRY-IN\ (CLOCK ENABLE\), BINARY/DECADE, UP/DOWN, PRESET ENABLE, and four individual JAN signals, Q1, Q2, Q3, Q4 and a CARRY OUT\ signal are provided as outputs.

A high PRESET ENABLE signal allows information on the JAM INPUTS to preset the counter to any state asynchronously with the clock. A low on each JAM line, when the PRESET-ENABLE signal is high, resets the counter to its zero count. The counter is advanced one count at the positive transition of the clock when the CARRY-IN\ and PRESET ENALBE signals are low. Advancement is inhibited when the CARRY-IN\ or PRESET ENABLE signals are high. The CARRY-OUT\ signal is normally high and goes low when the counter reaches its maximum count in the UP mode or the minimum count in the DOWN mode provided the CARRY-IN\ signal is low. The CARRY-IN\ signal in the low state can thus be considered a CLOCK ENABLE\. The CARRY-IN\ terminal must be connected to V_SS when not in use.

Binary counting is accomplished when the BINARY/DECADE input is high; the counter counts in the decade mode when the BINARY/DECADE input is low. The counter counts up when the UP/DOWN input is high, and down when the UP/DOWN input is low. Multiple packages can be connected in either a parallel-clocking or a ripple-clocking arrangement as shown in Fig. 17.

Parallel clocking provides synchronous control and hence faster response from all counting outputs. Ripple-clocking allows for longer clock input rise and fall times.

The CD4029B-series types are supplied in 16-lead hermetic dual-in-line ceramic packages (F3A suffix), 16-lead dual-in-line plastic packages (E suffix), 16-lead small-outline packages (M, M96, MT and NSR suffixes), and 16-lead thin shrink small-outline packages (PW and PWR suffixes).

Products containing the "CD4029B" keyword are: CD4029BCJ , CD4029BCN , CD4029BCSJ , CD4029BCWM , CD4029BCWMX , CD4029BD , CD4029BD-3 , CD4029BDMSR , CD4029BDNSR , CD4029BE , CD4029BE , CD4029BEE4 , CD4029BEE4 , CD4029BEG4 , CD4029BEX , CD4029BF , CD4029BF/3 , CD4029BF/3A , CD4029BF3 , CD4029BF3A

• Medium-speed operation… 8 MHz (typ.) @ C_L = 50 pF and V_DD–V_SS = 10 V
• Multi-package parallel clocking for synchronous high speed output response or ripple clocking for slow clock input rise and fall times
• "Preset Enable" and individual "Jam" inputs provided
• Binary or decade up/down counting
• BCD outputs in decade mode
• 100% tested for quiescent current at 20 V
• 5-V, 10-V, and 15-V parametric ratings
• Standardized, symmetrical output characteristics
• Maximum input current of 1 µA at 18 V over full package-temperature range; 100 nA at 18 V and 25°C
• Noise margin (full package-temperature range) =
          1 V at V_DD = 5 V
          2 V at V_DD = 10 V
       2.5 V at V_DD = 15 V
• Meets all requirements of JEDEC Tentative Standard No. 13B, "Standard Specifications for Description of ’B’ Series CMOS Devices"
• Applications:
  • Programmable binary and decade counting/frequency synthesizers-BCD output
  • Analog to digital and digital to analog conversion
  • Up/Down binary counting
  • Magnitude and sign generation
  • Up/Down decade counting
  • Difference counting