SN74AUP1G80 - Low-Power Single Postitive-Edge-Triggered D-Type Flip-Flop

Updated : 2020-01-09 14:39:16
Description

The AUP family is TI’s premier solution to the industry’s low-power needs inbattery-powered portable applications. This family assures a low static- and dynamic-powerconsumption across the entire VCC range of 0.8 V to 3.6 V, resulting inincreased battery life (see AUP – The Lowest-Power Family). This product also maintains excellentsignal integrity (see Excellent Signal Integrity).

This is a single positive-edge-triggered D-type flip-flop. When data at the data (D)input meets the setup time requirement, the data is transferred to the Qoutput on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage leveland is not directly related to the rise time of the clock pulse. Following the hold-time interval,data at the D input can be changed without affecting the levels at the outputs.

NanoStar™ package technology is a major breakthrough in IC packaging concepts, using thedie as the package.

This device is fully specified for partial-power-down applications usingIoff. The Ioff circuitry disables the outputs whenthe device is powered down. This inhibits current backflow into the device which prevents damage tothe device.

Products containing the "SN74AUP1G80" keyword are: SN74AUP1G80DBV , SN74AUP1G80DBVR , SN74AUP1G80DBVR , SN74AUP1G80DBVRG4 , SN74AUP1G80DBVRG4 , SN74AUP1G80DBVT , SN74AUP1G80DBVT , SN74AUP1G80DBVTG4 , SN74AUP1G80DBVTG4 , SN74AUP1G80DCKR , SN74AUP1G80DCKR , SN74AUP1G80DCKRE4 , SN74AUP1G80DCKRE4 , SN74AUP1G80DCKRG4 , SN74AUP1G80DCKRG4 , SN74AUP1G80DCKRTI , SN74AUP1G80DCKT , SN74AUP1G80DCKT , SN74AUP1G80DCKTG4 , SN74AUP1G80DCKTG4
Features

  • Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
  • ESD Performance Tested Per JESD 22
    • 2000-V Human-Body Model
      (A114-B, Class II)
    • 1000-V Charged-Device Model (C101)
  • Available in the Texas Instruments NanoStar™ Package
  • Low Static-Power Consumption
    (ICC = 0.9 µA Maximum)
  • Low Dynamic-Power Consumption
    (Cpd = 4.3 pF Typical at 3.3 V)
  • Low Input Capacitance (Ci = 1.5 pF Typical)
  • Low Noise – Overshoot and Undershoot <10% of VCC
  • Ioff Supports Partial-Power-Down Mode Operation
  • Schmitt-Trigger Action Allows Slow Input Transition and Better Switching Noise Immunity at the Input
    (Vhys = 250 mV Typical at 3.3 V)
  • Wide Operating VCC Range of 0.8 V to 3.6 V
  • Optimized for 3.3-V Operation
  • 3.6-V I/O Tolerant to Support Mixed-Mode Signal Operation
  • tpd = 4.4 ns Maximum at 3.3 V
  • Suitable for Point-to-Point Applications

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