SN74ALVTH32373 - 2.5-V/3.3-V 32-Bit Transparent D-Type Latches With 3-State Outputs

The \x92ALVTH32373 devices are 32-bit transparent D-type latches with 3-state outputs designed for 2.5-V or 3.3-V V_CC operation, but with the capability to provide a TTL interface to a 5-V system environment. These devices are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers.

These devices can be used as four 8-bit latches, two 16-bit latches, or one 32-bit latch. When the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is taken low, the Q outputs are latched at the levels set up at the D inputs.

A buffered output-enable (OE\) input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without interface or pullup components.

OE\ does not affect internal operations of the latch. Old data can be retained or new data can be entered while the outputs are in the high-impedance state.

Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of these devices as translators in a mixed 3.3-V/5-V system environment.

These devices are fully specified for hot-insertion applications using I_off and power-up 3-state. The I_off circuitry disables the outputs, preventing damaging current backflow through the devices when they are powered down. The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down, which prevents driver conflict.

When V_CC is between 0 and 1.2 V, the devices are in the high-impedance state during power up or power down. However, to ensure the high-impedance state above 1.2 V, OE\ should be tied to V_CC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.

The SN54ALVTH32373 is characterized for operation over the full military temperature range of \x9655°C to 125°C. The SN74ALVTH32373 is characterized for operation from \x9640°C to 85°C.

Products containing the "SN74ALVTH32373" keyword are: SN74ALVTH32373KR , SN74ALVTH32373KR

• State-of-the-Art Advanced BiCMOS Technology (ABT) Widebus+™ Design for 2.5-V and 3.3-V Operation and Low Static-Power Dissipation
• Support Mixed-Mode Signal Operation (5-V Input and Output Voltages With 2.3-V to 3.6-V V_CC)
• Typical V_OLP (Output Ground Bounce)
  <0.8 V at V_CC = 3.3 V, T_A = 25°C
• High Drive (\x9624/24 mA at 2.5-V and \x9632/64 mA at 3.3-V V_CC)
• I_off and Power-Up 3-State Support Hot Insertion
• Use Bus Hold on Data Inputs in Place of External Pullup/Pulldown Resistors to Prevent the Bus From Floating
• Auto3-State Eliminates Bus Current Loading When Output Exceeds V_CC + 0.5 V
• Flow-Through Architecture Facilitates Printed Circuit Board Layout
• Distributed V_CC and GND Pins Minimize High-Speed Switching Noise
• Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
• ESD Protection Exceeds JESD 22
  • 2000-V Human-Body Model (A114-A)
  • 200-V Machine Model (A115-A)
  • 1000-V Charged-Device Model (C101)
• Packaged in Plastic Fine-Pitch Ball Grid Array Package

NOTE: For tape and reel order entry:
The GKER package is abbreviated to KR.
Widebus+ is a trademark of Texas Instruments.