SN74ALVCH16821 - 3.3-V 20-Bit Bus-Interface Flip-Flop with 3-State Outputs

This 20-bit bus-interface flip-flop is designed for 1.65-V to 3.6-V V_CC operation.

The SN74ALVCH16821 can be used as two 10-bit flip-flops or one 20-bit flip-flop. The 20 flip-flops are edge-triggered D-type flip-flops. On the positive transition of the clock (CLK) input, the device provides true data at the Q outputs.

A buffered output-enable (OE)\ input can be used to place the ten outputs in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without need for interface or pullup components.

OE\ does not affect the internal operation of the flip-flops. Old data can be retained or new data can be entered while the outputs are in the high-impedance state.

To ensure the high-impedance state during power up or power down, OE\ should be tied to V_CC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended.

Products containing the "SN74ALVCH16821" keyword are: SN74ALVCH16821DGG , SN74ALVCH16821DGGE4 , SN74ALVCH16821DGGR , SN74ALVCH16821DGGR , SN74ALVCH16821DGGRG4 , SN74ALVCH16821DL , SN74ALVCH16821DL , SN74ALVCH16821DLR , SN74ALVCH16821DLR

• Member of the Texas Instruments Widebus™ Family
• Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors
• Latch-Up Performance Exceeds 250 mA Per JESD 17
• ESD Protection Exceeds JESD 22
  • 2000-V Human-Body Model (A114-A)
  • 200-V Machine Model (A115-A)

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