This 10-bit flip-flop is designed for 1.65-V to 3.6-V VCC operation.
The flip-flops of the SN74ALVCH16820 are edge-triggered D-type flip-flops. On the positive transition of the clock (CLK) input, the device provides true data at the Q outputs.
A buffered output-enable (OE)\ input can be used to place the ten outputs in either a normal logic state (high or low logic level) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without need for interface or pullup components.
OE\ input does not affect the internal operation of the flip-flops. Old data can be retained or new data can be entered while the outputs are in the high-impedance state.
To ensure the high-impedance state during power up or power down, OE\ should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
Active bus-hold circuitry is provided to hold unused or undriven inputs at a valid logic level. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended.
Products containing the "SN74ALVCH16820" keyword are: SN74ALVCH16820DGGR , SN74ALVCH16820DGGR , SN74ALVCH16820DGGRG4 , SN74ALVCH16820DL , SN74ALVCH16820DLR , SN74ALVCH16820DLRG4Widebus is a trademark of Texas Instruments.
Status | ACTIVE |
SubFamily | D-type flip-flop |
Technology Family | ALVC |
VCC | 3.6 |
Bits | 10 |
Voltage | 1.8^2.5^2.7^3.3 |
F @ nom voltage | 150 |
ICC @ nom voltage | 0.04 |
tpd @ Nom Voltage | 5.9^5.5^4.8 |
3-state output | Yes |
Rating | Catalog |
Operating temperature range | -40 to 85 |
Package Group | TSSOP|56 |
Package size: mm2:W x L (PKG) | [pf]56TSSOP[/pf]: 113 mm2: 8.1 x 14 (TSSOP|56) |
Approx. price | 1.82 | 1ku |