The SN74AHC595 contains an 8-bit serial-in, parallel-out shift register that feeds an 8-bit D-type storage register. The storage register has parallel 3-state outputs. Separate clocks are provided for both the shift and storage registers. The shift register has a direct overriding clear (SRCLR) input, serial (SER) input, and a serial output for cascading. When the output-enable (OE) input is high, all outputs, except QH', are in the high-impedance state.
Both the shift-register clock (SRCLK) and storage-register clock (RCLK) are positive-edge triggered. If both clocks are connected together, the shift register always is one clock pulse ahead of the storage register.
| Status | ACTIVE |
| SubFamily | Shift register |
| Technology Family | AHC |
| VCC | 5.5 |
| Bits | 8 |
| Voltage | 3.3^5 |
| F @ nom voltage | 110 |
| ICC @ nom voltage | 0.04 |
| tpd @ Nom Voltage | 20^13.5 |
| 3-state output | Yes |
| Rating | Automotive |
| Operating temperature range | -40 to 125 |
| Package Group | TSSOP|16 |
| Package size: mm2:W x L (PKG) | [pf]16TSSOP[/pf]: 22 mm2: 4.4 x 5 (TSSOP|16) |
| Approx. price | 0.16 | 1ku |