CD4724B 8-bit addressable latch is a serial-input, parallel-output storage register that can perform a variety of functions.
Data are inputted to a particular bit in the latch when that bit is addressed (by means of input A0, A1, A2) and when WRITE DISABLE is at a low level. When WRITE DISABLE is high, data entry is inhibited; however, all 8 outputs can be continuously read independent of WRITE DISABLE and address inputs.
A master RESET input is available, which resets all bits to a logic "0" level when RESET and WRITE DISABLE are at a high level. When RESET is at a high level, and WRITE RESET is at a low level, the latch acts as a 1-of-8 demultiplexer; the bit that is addressed has an active output which follows the data input, while all unaddressed bits are held to a logic "0" level.
The CD4724B types are supplied in 16-lead hermetic dual-in-line ceramic packages (F3A suffix), 16-lead dual-in-line plastic packages (E suffix), 16-lead small-outline packages (NSR suffix), and 16-lead thin shrink small-outline packages (PW and PWR suffixes).
Products containing the "CD4724B" keyword are: CD4724B , CD4724BCJ , CD4724BCM , CD4724BCMX , CD4724BCN , CD4724BCN , CD4724BCN NS , CD4724BCN-MM4724BCN , CD4724BD , CD4724BDM , CD4724BE , CD4724BE , CD4724BE. , CD4724BEE4 , CD4724BEG4 , CD4724BEX , CD4724BF , CD4724BF3A , CD4724BFX , CD4724BM1NOT RECOMMENDED FOR NEW DESIGNS SEE CD4099B
Status | NRND |
SubFamily | Other latch |
Technology Family | CD4000 |
VCC | 18 |
Bits | 8 |
Voltage | 10 |
F @ nom voltage | 8 |
ICC @ nom voltage | 0.3 |
tpd @ Nom Voltage | 150 |
3-state output | No |
Rating | Catalog |
Operating temperature range | -55 to 125 |
Package Group | PDIP|16 |
Package size: mm2:W x L (PKG) | See datasheet (PDIP) |
Approx. price | 0.49 | 1ku |