CD4042B types contain four latch circuits, each strobed by a common clock. Complementary buffered outputs are available from each circuit. The impedance of the n- and p-channel output devices is balanced and all outputs are electrically identical.
Information present at the data input is transferred to outputs Q and Q\ during the CLOCK level which is programmed by the POLARITY input. For POLARITY = 0 the transfer occurs during the 0 CLOCK level and for POLARITY = 1 the transfer occurs during the 1 CLOCK level. The outputs follow the data input providing the CLOCK and POLARITY levels defined above are present. When a CLOCK transition occurs (positive for POLARITY = 0 and negative for POLARITY = 1) the information present at the input during the CLOCK transition is retained at the output until an opposite CLOCK transition occurs.
The CD4042B types are supplied in 16-lead hermetic dual-in-line ceramic packages (F3A suffixes), 16-lead dual-in-line plastic package (E suffix), 16-lead small-outline packages (D, DR, DT, DW, DWR, and NSR suffixes), and 16-lead thin shrink small-outline packages (PW and PWR suffixes).
Products containing the "CD4042B" keyword are: CD4042B , CD4042BCJ , CD4042BCM , CD4042BCN , CD4042BCN(MM5642BN) , CD4042BD , CD4042BD , CD4042BD/3 , CD4042BDE4 , CD4042BDE4 , CD4042BDG4 , CD4042BDMSR , CD4042BDR , CD4042BDR , CD4042BDR/SOP , CD4042BDRCD4043BDR , CD4042BDRE4 , CD4042BDRG4 , CD4042BDRG4 , CD4042BDTData sheet acquired from Harris Semiconductor
Status | ACTIVE |
SubFamily | Other latch |
Technology Family | CD4000 |
VCC | 18 |
Bits | 4 |
Voltage | 10 |
F @ nom voltage | 8 |
ICC @ nom voltage | 0.06 |
tpd @ Nom Voltage | 200 |
3-state output | No |
Rating | Catalog |
Operating temperature range | -55 to 125 |
Package Group | PDIP|16 |
Package size: mm2:W x L (PKG) | See datasheet (PDIP) |
Approx. price | 0.12 | 1ku |