SN74LV244AT - Octal Buffer/Driver With 3-State Outputs

This octal buffer/driver is designed specifically to improve both the performance and density of 3-state memory-address drivers, clock drivers, and bus-oriented receivers and transmitters.

The SN74LV244AT is organized as two 4-bit buffers/line drivers with separate output-enable (OE) inputs. When OE is low, the device passes data from the A inputs to the Y outputs. When OE is high, the outputs are in the high-impedance state.

To ensure the high-impedance state during power up or power down, OE shall be tied to V_CC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

This device is fully specified for partial-power-down applications using I_off. The I_off circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

Products containing the "SN74LV244AT" keyword are: SN74LV244ATDBRE4 , SN74LV244ATDBRE4 , SN74LV244ATDBRG4 , SN74LV244ATDBRG4 , SN74LV244ATDGVR , SN74LV244ATDGVRE4 , SN74LV244ATDGVRE4 , SN74LV244ATDGVRG4 , SN74LV244ATDW , SN74LV244ATDW , SN74LV244ATDWE4 , SN74LV244ATDWE4 , SN74LV244ATDWR , SN74LV244ATDWR , SN74LV244ATNS , SN74LV244ATNS , SN74LV244ATNSR , SN74LV244ATPW , SN74LV244ATPW , SN74LV244ATPWG4

• Inputs Are TTL-Voltage Compatible
• 4.5-V to 5.5-V V_CC Operation
• Typical t_pd = 5.4 ns at 5 V
• Typical V_OLP (Output Ground Bounce)
  <0.8 V at V_CC = 5 V, T_A = 25°C
• Typical V_OHV (Output V_OH Undershoot)
  >2.3 V at V_CC = 5 V, T_A = 25°C
• Supports Mixed-Mode Voltage Operation on All Ports
• I_off Supports Partial-Power-Down Mode Operation
• Latch-Up Performance Exceeds 250 mA Per JESD 17
• ESD Protection Exceeds JESD 22
  • 2000-V Human-Body Model (A114-A)
  • 200-V Machine Model (A115-A)
  • 1000-V Charged-Device Model (C101)