The SN74LV125A-Q1 quadruple bus buffer gate is designed for 2-V to 5.5-V VCC operation.
This device features independent line drivers with 3-state outputs. Each output is disabled when the associated output-enable (OE) input is high.
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
These devices are fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the devices when they are powered down.
| Status | ACTIVE |
| SubFamily | Non-Inverting buffer/driver |
| Technology Family | LV-A |
| VCC | 5.5 |
| Bits | 4 |
| Voltage | 2.5^3.3^5 |
| F @ nom voltage | 110 |
| tpd @ Nom Voltage | 16.5^11.5^7.5 |
| ICC @ nom voltage | 0.02 |
| IOL | 50 |
| IOH | -50 |
| Rating | Automotive |
| Operating temperature range | -40 to 125 |
| Package Group | VQFN|14 |
| Package size: mm2:W x L (PKG) | [pf]14VQFN[/pf]: 12 mm2: 3.5 x 3.5 (VQFN|14) |
| Approx. price | 0.11 | 1ku |