These octal buffers and line drivers are designed specifically to improve both the performance and density of 3-state memory address drivers, clock drivers, and bus-oriented receivers and transmitters. The HC240 devices are organized as two 4-bit buffers/drivers with separate output-enable (OE)\ inputs. When OE\ is low, the device passes inverted data from the A inputs to the Y outputs. When OE\ is high, the outputs are in the high-impedance state.
Products containing the "SN74HC240" keyword are: SN74HC240AN , SN74HC240ANSR , SN74HC240ANSR , SN74HC240APW , SN74HC240APWG4 , SN74HC240APWR , SN74HC240APWR , SN74HC240APWRG4 , SN74HC240DBR , SN74HC240DBR , SN74HC240DBRE4 , SN74HC240DBRG4 , SN74HC240DW , SN74HC240DW , SN74HC240DWE4 , SN74HC240DWE4 , SN74HC240DWG4 , SN74HC240DWG4 , SN74HC240DWR , SN74HC240DWR| Status | ACTIVE |
| SubFamily | Inverting buffer/driver |
| Technology Family | HC |
| VCC | 6 |
| Bits | 8 |
| Voltage | 5 |
| F @ nom voltage | 20 |
| tpd @ Nom Voltage | 38 |
| ICC @ nom voltage | 0.08 |
| IOL | 6 |
| IOH | -6 |
| Rating | Catalog |
| Operating temperature range | -40 to 85 |
| Package Group | PDIP|20 |
| Package size: mm2:W x L (PKG) | See datasheet (PDIP) |
| Approx. price | 0.12 | 1ku |