SN74AUC2G34 - Dual Buffer Gate

This dual buffer gate is operational at 0.8-V to 2.7-V V_CC, but is designed specifically for 1.65-V to 1.95-V V_CC operation.

The SN74AUC2G34 performs the Boolean function Y = A in positive logic.

NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the package.

This device is fully specified for partial-power-down applications using I_off. The I_off circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

Products containing the "SN74AUC2G34" keyword are: SN74AUC2G34DBVR , SN74AUC2G34DBVR , SN74AUC2G34DBVRG4 , SN74AUC2G34DCKR , SN74AUC2G34DCKRE4 , SN74AUC2G34DCKRE4 , SN74AUC2G34DCKRG4 , SN74AUC2G34DRLR , SN74AUC2G34DRLR , SN74AUC2G34DRLRG4 , SN74AUC2G34DRLRG4 , SN74AUC2G34YEPR , SN74AUC2G34YEPR , SN74AUC2G34YZPR , SN74AUC2G34YZPR , SN74AUC2G34YZPR/47SU97 , SN74AUC2G34YZTR , SN74AUC2G34YZTR

• Available in the Texas Instruments NanoFree™ Package
• Optimized for 1.8-V Operation and Is 3.6-V I/O Tolerant to Support Mixed-Mode Signal Operation
• I_off Supports Partial-Power-Down Mode Operation
• Sub-1-V Operable
• Max t_pd of 1.6 ns at 1.8 V
• Low Power Consumption, 10 µA at 1.8 V
• ±8-mA Output Drive at 1.8 V
• Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
• ESD Protection Exceeds JESD 22
  • 2000-V Human-Body Model (A114-A)
  • 200-V Machine Model (A115-A)
  • 1000-V Charged-Device Model (C101)

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