SN74AUC125 - Quadruple Bus Buffer Gate with 3-State Outputs

This quadruple bus buffer gate is designed for 0.8-V to 2.7-V V_CC operation, but is designed specifically for 1.6-V to 1.95-V V_CC operation.

The SN74AUC125 contains four independent line drivers with 3-state outputs. Each output is disabled when the associated output-enable (OE) input is high.

To ensure the high-impedance state during power up or power down, OE should be tied to V_CC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

This device is fully specified for partial-power-down applications using I_off. The I_off circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

Products containing the "SN74AUC125" keyword are: SN74AUC125RGYR , SN74AUC125RGYR , SN74AUC125RGYR(MS125) , SN74AUC125RGYR/MS125 , SN74AUC125RGYRG4 , SN74AUC125RGYRG4

• Optimized for 1.8-V Operation and Is 3.6-V I/O Tolerant to Support Mixed-Mode Signal Operation
• I_off Supports Partial-Power-Down Mode Operation
• Sub-1-V Operable
• Max t_pd of 2.1 ns at 1.8 V
• Low Power Consumption, 10-µA Max I_CC
• ±8-mA Output Drive at 1.8 V
• Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
• ESD Protection Exceeds JESD 22
  • 2000-V Human-Body Model (A114-A)
  • 200-V Machine Model (A115-A)
  • 1500-V Charged-Device Model (C101)