These octal buffers/drivers are designed specifically to improve the performance and density of 3-state memory-address drivers, clock drivers, and bus-oriented receivers and transmitters.
The ’AHC240 devices are organized as two 4-bit buffers/line drivers with separate output-enable (OE)\ inputs. When OE\ is low, the device passes data from the A inputs to the Y outputs. When OE\ is high, the outputs are in the high-impedance state.
To ensure the high-impedance state during power up or power down, OE\ should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
Products containing the "SN74AHC240" keyword are: SN74AHC240DBR , SN74AHC240DBR , SN74AHC240DBR HA240 , SN74AHC240DBRE4 , SN74AHC240DBRG4 , SN74AHC240DBRG4 , SN74AHC240DGVR , SN74AHC240DGVRG4 , SN74AHC240DW , SN74AHC240DW , SN74AHC240DWR , SN74AHC240DWR , SN74AHC240DWRG4 , SN74AHC240N , SN74AHC240N , SN74AHC240NS , SN74AHC240NSR , SN74AHC240NSR , SN74AHC240PW , SN74AHC240PW| Status | ACTIVE |
| SubFamily | Inverting buffer/driver |
| Technology Family | AHC |
| VCC | 5.5 |
| Bits | 8 |
| Voltage | 3.3^5 |
| F @ nom voltage | 110 |
| tpd @ Nom Voltage | 12.5^8.5 |
| ICC @ nom voltage | 0.04 |
| IOL | 8 |
| IOH | -8 |
| Rating | Catalog |
| Operating temperature range | -40 to 85 |
| Package Group | PDIP|20 |
| Package size: mm2:W x L (PKG) | See datasheet (PDIP) |
| Approx. price | 0.12 | 1ku |