This triple 3-input positive-NAND gate is designed for 1.65-V to 3.6-V VCC operation.
The SN74LVC10A performs the Boolean function Y = A B C or Y = A + B + C in positive logic.
Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of these devices as translators in a mixed 3.3-V/5-V system environment.
Products containing the "SN74LVC10A" keyword are: SN74LVC10AD , SN74LVC10AD , SN74LVC10ADBR , SN74LVC10ADBR , SN74LVC10ADBRE4 , SN74LVC10ADBRE4 , SN74LVC10ADG4 , SN74LVC10ADG4 , SN74LVC10ADR , SN74LVC10ADR , SN74LVC10ADR SOP3.9 , SN74LVC10ADRG4 , SN74LVC10ADRG4 , SN74LVC10ADRG4 (PB) , SN74LVC10ADT , SN74LVC10ADT , SN74LVC10ANSR , SN74LVC10ANSR , SN74LVC10APW , SN74LVC10APW| Status | ACTIVE |
| SubFamily | NAND gate |
| Technology Family | LVC |
| VCC | 3.6 |
| Channels | 3 |
| Inputs per channel | 3 |
| ICC @ nom voltage | 0.04 |
| IOL | 24 |
| IOH | -24 |
| Input type | Standard CMOS |
| Output type | Push-Pull |
| Features | Partial Power Down (Ioff)^Over-Voltage Tolerant Inputs^Ultra High Speed (tpd <5ns) |
| Data rate | 100 |
| Rating | Catalog |
| Operating temperature range | -40 to 125 |
| Package Group | SOIC|14 |
| Package size: mm2:W x L (PKG) | [pf]14SO[/pf]: 80 mm2: 7.8 x 10.2 (SO|14) |
| Approx. price | 0.08 | 1ku |