THS4552 - Dual Channel, Low-Noise, Precision, 150-MHz, Fully Differential Amplifier

Updated : 2020-01-09 14:16:51
Description

The THS4552 fully differential amplifier offers an easy interface from single-endedsources to the differential output required by high-precision analog-to-digital converters (ADCs).Designed for exceptional dc accuracy, low noise, and robust capacitive load driving, this device iswell suited for data acquisition systems where high precision is required along with the bestsignal-to-noise ratio (SNR) and spurious-free dynamic range (SFDR) through the amplifier and ADCcombination.

The THS4552 features the negative rail input required when interfacing a dc-coupled,ground-centered, source signal to a single-supply differential input ADC. Very low dc error anddrift terms support the emerging 16- to 20-bit successive-approximation register (SAR) inputrequirements. A wide-range output common-mode control supports the ADC running from 1.8-V to 5-Vsupplies with ADC common-mode input requirements from 0.7 V to greater than3.0 V.

The THS4552 device is characterized for operation over the wide temperature range of–40°C to +125°C, and is available in 16-pin TSSOP and 24-pin VQFN packages.



Products containing the "THS4552" keyword are: THS4552IPWR , THS4552IPWR , THS4552IPWT , THS4552IPWT , THS4552IRTWR , THS4552IRTWR , THS4552IRTWT , THS4552IRTWT , THS4552PWEVM , THS4552RTWEVM , THS4552RTWEVM
Features

  • Bandwidth: 150 MHz (G = 1 V/V)
  • Differential Output Slew Rate: 220 V/µs
  • Gain Bandwidth Product: 135 MHz
  • Negative Rail Input (NRI),
    Rail-to-Rail Output (RRO)
  • Wide Output Common-Mode Control Range
  • Single-Supply Operating Range: 2.7 V to 5.4 V
  • Trimmed-Supply Current:
    1.37 mA per Channel at 5 V
  • 25°C Input Offset: ±175 µV (max)
  • Input Offset Voltage Drift: ±2.0 µV/°C (max)
  • Differential Input Voltage Noise: 3.3 nV/√Hz
  • HD2: –128 dBc at 2 VPP, 100 kHz
  • HD3: –139 dBc at 2 VPP, 100 kHz
  • < 50-ns Settling Time: 4-V Step to 0.01%
  • 18-Bit Settling Time: 4-V Step, < 500 ns

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