CDCLVP111-SP - 1:10 High Speed Clock Buffer with Selectable Input Clock Driver

The CDCLVP111-SP clock driver distributes one differential clock pair of LVPECL input, (CLK0, CLK1) to ten pairs of differential LVPECL clock (Q0, Q9) outputs with minimum skew for clock distribution. The CDCLVP111-SP can accept two clock sources into an input multiplexer. The CDCLVP111-SP is specifically designed for driving 50-Ω transmission lines. When an output pin is not used, leaving it open is recommended to reduce power consumption. If only one of the output pins from a differential pair is used, the other output pin must be identically terminated to 50 Ω.

The V_BB reference voltage output is used if single-ended input operation is required. In this case, the V_BB pin should be connected to CLK0 and bypassed to GND via a 10-nF capacitor.

For high-speed performance, the differential mode is strongly recommended.

The CDCLVP111-SP is characterized for operation from –55°C to 125°C.

• Distributes One Differential Clock Input Pair LVPECL to 10 Differential LVPECL
• Fully Compatible With LVECL and LVPECL
• Supports a Wide Supply Voltage Range From 2.375 V to 3.8 V
• Selectable Clock Input Through CLK_SEL
• Low-Output Skew (Typical 15 ps) for Clock-Distribution Applications
  • Additive Jitter Less Than 1 ps
  • Propagation Delay Less Than 355 ps
  • Open Input Default State
  • LVDS, CML, SSTL input Compatible
• V_BB Reference Voltage Output for Single-Ended Clocking
• Frequency Range From DC to 3.5 GHz
• Supports Defense, Aerospace, and Medical Applications
  • Controlled Baseline
  • One Assembly and Test Site
  • One Fabrication Site
  • Available in Military (–55°C to 125°C) Temperature Range⁽¹⁾
  • Extended Product Life Cycle
  • Extended Product-Change Notification
  • Product Traceability