The CDC339 is a high-performance, low-skew clock driver. It is specifically designed for applications requiring synchronized output signals at both the primary clock frequency and one-half the primary clock frequency. The four Y outputs switch in phase and at the same frequency as the clock (CLK) input. The four Q outputs switch at one-half the frequency of CLK.
When the output-enable ( ) input is low and the clear () input is high, the Y outputs follow CLK and the Q outputs toggle on low-to-high transitions of CLK. Taking low asynchronously resets the Q outputs to the low level. When is high, the outputs are in the high-impedance state.
The CDC339 is characterized for operation from -40°C to 85°C.
Products containing the "CDC339" keyword are: CDC339 , CDC339DB , CDC339DB , CDC339DBG4 , CDC339DBG4 , CDC339DBLE , CDC339DBR , CDC339DBR CK339 , CDC339DBRG4 , CDC339DBRG4 , CDC339DW , CDC339DW , CDC339DWG4 , CDC339DWG4 , CDC339DWR , CDC339DWRG4 , CDC339NS , CDC339NSREPIC-IIB is a trademark of Texas Instruments Incorporated.
Status | ACTIVE |
SubFamily | Dividers^Single-ended |
Additive RMS jitter | N/A |
Output frequency | 80 |
Input level | TTL |
Number of outputs | 8 |
Output level | TTL |
VCC | 5 |
VCC out | 5 |
Input frequency | 80 |
Operating temperature range | -40 to 85 |
Package Group | SOIC|20 |
Package size: mm2:W x L (PKG) | [pf]20SOIC[/pf]: 132 mm2: 10.3 x 12.8 (SOIC|20) |
Rating | Catalog |
Approx. price | 6.43 | 1ku |