CDC208 - 5V Dual 1-to-4 clock driver

The CDC208 contains dual clock-driver circuits that fanout one input signal to four outputs with minimum skew for clock distribution (see Figure 2). The device also offers two output-enable (OE1\ and OE2\) inputs for each circuit that can force the outputs to be disabled to a high-impedance state or to a high- or low-logic level independent of the signal on the respective A input.

Skew parameters are specified for a reduced temperature and voltage range common to many applications.

The CDC208 is characterized for operation from -40°C to 85°C.

Products containing the "CDC208" keyword are: CDC208 , CDC208DBLE , CDC208DBR CK208 , CDC208DW , CDC208DW , CDC208DWG4 , CDC208DWR , CDC208DWR , CDC208DWR G4 , CDC208DWRG4 , CDC208DWRG4 , CDC208N , CDC208N , SCS140P , CDC208NS , CDC208NS , CDC208NSG4 , CDC208NSG4 , CDC208NSR , CDC208NSR , CDC208NSRG4

• Low-Skew Propagation Delay Specifications for Clock-Driver Applications
• TTL-Compatible Inputs and CMOS-Compatible Outputs
• Flow-Through Architecture Optimizes
  PCB Layout
• Center-Pin V_CC and GND Pin Configurations Minimize High-Speed Switching Noise
• EPIC^TM (Enhanced-Performance Implanted CMOS) 1-um Process
• 500-mA Typical Latch-Up Immunity at 125°C
• Package Options Include Plastic Small-Outline (DW)

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