This octal bus transceiver and register is designed for 1.65-V to 3.6-V VCC operation.
The SN74LVC2952A consists of two 8-bit back-to-back registers that store data flowing in both directions between two bidirectional buses. Data on the A or B bus is stored in the registers on the low-to-high transition of the clock (CLKAB or CLKBA) input, provided that the clock-enable (CLKENAB\ or CLKENBA)\ input is low. Taking the output-enable (OEAB\ or OEBA)\ input low accesses the data on either port.
Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of these devices as translators in a mixed 3.3-V/5-V system environment.
To ensure the high-impedance state during power up or power down, OE\ should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.
Products containing the "SN74LVC2952A" keyword are: SN74LVC2952ADBR , SN74LVC2952ADBR , SN74LVC2952ADBRG4 , SN74LVC2952ADW , SN74LVC2952ADW , SN74LVC2952ADWR , SN74LVC2952ADWR , SN74LVC2952ANSRG4 , SN74LVC2952APW , SN74LVC2952APW , SN74LVC2952APWR , SN74LVC2952APWR , SN74LVC2952APWRG4 , SN74LVC2952APWTStatus | ACTIVE |
SubFamily | Registered transceiver |
Technology Family | LVC |
VCC | 3.6 |
Bits | 8 |
Voltage | 1.8^2.5^2.7^3.3 |
F @ nom voltage | 100 |
tpd @ Nom Voltage | 8.8^8.2 |
IOL | 24 |
Rating | Catalog |
Operating temperature range | -40 to 85 |
Package Group | SSOP|24 |
Package size: mm2:W x L (PKG) | [pf]24SSOP[/pf]: 64 mm2: 7.8 x 8.2 (SSOP|24) |
Approx. price | 0.41 | 1ku |
Schmitt Trigger | No |