The DAC161S055 is a precision 16-bit, buffered voltage output Digital-to-Analog Converter (DAC) that operates from a 2.7V to 5.25V supply with a separate I/O supply pin that operates down to 1.7V. The on-chip precision output buffer provides rail-to-rail output swing and has a typical settling time of 5 µsec. The external voltage reference can be set between 2.5V and VA (the analog supply voltage), providing the widest dynamic output range possible.
The 4-wire SPI compatible interface operates at clock rates up to 20 MHz. The part is capable of Diasy Chain and Data Read Back. An on board power-on-reset (POR) circuit ensures the output powers up to a known state.
The DAC161S055 features a power-up value pin (MZB), a load DAC pin (LDACB) and a DAC clear (CLRB) pin. MZB sets the startup output voltage to either GND or mid-scale. LDACB updates the output, allowing multiple DACs to update their outputs simultaneously. CLRB can be used to reset the output signal to the value determined by MZB.
The DAC161S055 has a power-down option that reduces power consumption when the part is not in use. It is available in a 16-lead LLP package.
Products containing the "DAC161S055" keyword are: DAC161S055CISQ , DAC161S055CISQ/NOPB , DAC161S055CISQ/NOPB , DAC161S055CISQE , DAC161S055CISQE/NOPB , DAC161S055CISQE/NOPB , DAC161S055CISQX , DAC161S055CISQX/NOPB , DAC161S055EB , DAC161S055EB/NOPB , DAC161S055EB/NOPB , DAC161S055EVM| Status | ACTIVE |
| SubFamily | Precision DACs (<=10MSPS) |
| Resolution | 16 |
| Settling Time | 5 |
| Sample / Update Rate | 0.08 |
| DAC channels | 1 |
| Architecture | R-2R |
| Power consumption | 5.5 |
| Interface | SPI |
| INL | 3 |
| Reference: type | Ext |
| Output type | Buffered Voltage |
| Rating | Catalog |
| Operating temperature range | -40 to 105 |
| Package Group | WQFN|16 |
| Package size: mm2:W x L (PKG) | [pf]16WQFN[/pf]: 16 mm2: 4 x 4 (WQFN|16) |
| Approx. price | 5.00 | 1ku |
| SFDR |