ADS5294 - Eight-Channel, 14-Bit, 80-MSPS Analog-to-Digital Converter (ADC)

The ADS5294 is a low-power 80-MSPS 8-Channel ADC that uses CMOS process technology andinnovative circuit techniques. Low power consumption, high SNR, low SFDR, and consistent overloadrecovery allow users to design high-performance systems.

The digital processing block of the ADS5294 integrates several commonly used digitalfunctions for improving system performance. The device includes a digital filter module that hasbuilt-in decimation filters (with lowpass, highpass and bandpass characteristics). The decimationrate is also programmable (by 2, by 4, or by 8). This rate is useful for narrow-band applications,where the filters are used to conveniently improve SNR and knock-off harmonics, while at the sametime reducing the output data rate. The device includes an averaging mode where two channels (oreven four channels) are averaged to improve SNR.

Serial LVDS outputs reduce the number of interface lines and enable the highest systemintegration. The digital data from each channel ADC is output over one or two wires of LVDS outputlines depending on the ADC sampling rate. This 2-wire interface maintains a low serial-data rate,allowing low-cost FPGA-based receivers to be used even at a high sample rate. The ADC resolution isprogrammed to 12-bit or 14-bit through registers. A unique feature is the programmable-mappingmodule that allows flexible mapping between the input channels and the LVDS output pins. Thismodule greatly reduces the complexity of LVDS-output routing, and by reducing the number of PCBlayers, potentially results in cheaper system boards.

The device integrates an internal reference trimmed to accurately match across devices.Internal reference mode achieves the best performance. External references can also drive thedevice.

The device is available in a 12-mm × 12-mm 80-pin QFP package. The device is specifiedover a –40°C to 85°C operating temperature range. ADS5294 is completely pin-to-pin and registercompatible to ADS5292.

• Maximum Sample Rate: 80 MSPS/14-Bit
• High Signal-to-Noise Ratio
  • 75.5-dBFS SNR at 5 MHz / 80 MSPS
  • 78.2-dBFS SNR at 5 MHz / 80 MSPS and Decimation Filter Enabled
  • 84-dBc SFDR at 5 MHz / 80 MSPS
• Low Power Consumption
  • 58 mW/CH at 50 MSPS
  • 77 mW/CH at 80 MSPS (2-LVDS Wire Per Channel)
• Digital Processing Block
  • Programmable FIR Decimation Filter and Oversampling to Minimize Harmonic Interference
  • Programmable IIR High-Pass Filter to Minimize DC Offset
  • Programmable Digital Gain: 0 dB to 12 dB
  • 2-Channel or 4-Channel Averaging
• Flexible Serialized LVDS Outputs:
  • One or Two Wires of LVDS Output Lines Per Channel Depending on ADC Sampling Rate
  • Programmable Mapping Between ADC Input Channels and LVDS Output Pins-Eases Board Design
  • Variety of Test Patterns to Verify Data Capture by FPGA/Receiver
• Internal and External References
• 1.8-V Operation for Low Power Consumption
• Low-Frequency Noise Suppression
• Recovery From 6-dB Overload Within 1 Clock Cycle
• Package: 12-mm × 12-mm 80-Pin QFP

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