ADC32RF44 - Dual-Channel, 14-Bit, 2.6-GSPS RF-Sampling Analog-to-Digital Converter (ADC)

The ADC32RF44 device is a 14-bit, 2.6-GSPS, dual-channel, analog-to-digital converter(ADC) that supports RF sampling with input frequencies up to 4 GHz and beyond.Designed for high signal-to-noise ratio (SNR), the ADC32RF44 delivers a noise spectral density of–154.2 dBFS/Hz as well as dynamic range and channel isolation over a large input frequency range.The buffered analog input with on-chip termination provides uniform input impedance across a widefrequency range and minimizes sample-and-hold glitch energy.

Each ADC channel can be connected to a dual-band, digital down-converter (DDC) with up tothree independent, 16-bit numerically-controlled oscillators (NCOs) per DDC for phase-coherentfrequency hopping. Additionally, the ADC is equipped with front-end peak and RMS power detectorsand alarm functions to support external automatic gain control (AGC) algorithms.

The ADC32RF44 supports the JESD204B serial interface with subclass 1-based deterministiclatency using data rates up to 12.5 Gbps with up to four lanes per ADC. The device is offered in a72-pin VQFN package (10 mm × 10 mm) and supports the industrial temperature range (–40°C to +85°C).

• 14-Bit, Dual-Channel, 2.6-GSPS ADC
• Noise Floor: –154.2 dBFS/Hz
• RF Input Supports Up to 4.0 GHz
• Aperture Jitter: 90 f_S
• Channel Isolation: 95 dB at f_IN = 1.8 GHz
• Spectral Performance (f_IN = 900 MHz, –2 dBFS):
  • SNR: 61.2 dBFS
  • SFDR: 65-dBc HD2, HD3
  • SFDR: 79-dBc Worst Spur
• Spectral Performance (f_IN = 1.85 GHz, –2 dBFS):
  • SNR: 58.3 dBFS
  • SFDR: 69-dBc HD2, HD3
  • SFDR: 74-dBc Worst Spur
• On-Chip Digital Down-Converters:
  • Up to 4 DDCs (Dual-Band Mode)
  • Up to 3 Independent NCOs per DDC
• On-Chip Input Clamp for Overvoltage Protection
• Programmable On-Chip Power Detectors with Alarm Pins for AGC Support
• On-Chip Dither
• On-Chip Input Termination
• Input Full-Scale: 1.35 V_PP
• Support for Multi-Chip Synchronization
• JESD204B Interface:
  • Subclass 1-Based Deterministic Latency
  • 4 Lanes Per Channel at 12.5 Gbps
• Power Dissipation: 2.95 W/Ch at 2.6 GSPS
• 72-Pin VQFN Package (10 mm × 10 mm)

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