ADC12DJ3200QML-SP - Space grade, 12-bit, dual 3.2-GSPS or single 6.4-GSPS, RF-sampling analog-to-digital converter (ADC)

The ADC12DJ3200QML-SP device is an RF-sampling, giga-sample, analog-to-digital converter(ADC) that can directly sample input frequencies from dc to above 10 GHz. In dual-channel mode, theADC12DJ3200QML-SP can sample up to 3200 MSPS. In single-channel mode, the device can sample up to6400 MSPS. Programmable tradeoffs in channel count (dual-channel mode) and Nyquist bandwidth(single-channel mode) allow development of flexible hardware that meets the needs of both highchannel count or wide instantaneous signal bandwidth applications. Full-power input bandwidth (–3dB) of 7.0 GHz, with usable frequencies exceeding the –3-dB point in both dual- and single-channelmodes, allows direct RF sampling of L-band, S-band, C-band, and X-band for frequency agilesystems.

The ADC12DJ3200QML-SP uses a high-speed JESD204B output interface with up to 16serialized lanes and subclass-1 compliance for deterministic latency and multidevicesynchronization. The serial output lanes support up to 12.8 Gbps, and can be configured to tradeoff bit rate and number of lanes. Innovative synchronization features, including noiseless aperturedelay (t_AD) adjustment and SYSREF windowing, simplify system design forsynthetic aperture radar (SAR) and phased-array MIMO communications. Optional digital downconverters (DDCs) in dual-channel mode allow for reduction in interface rate (real and complexdecimation modes) and digital mixing of the signal (complex decimation modes only).

• ADC Core:
  • 12-Bit Resolution
  • Up to 6.4 GSPS in Single-Channel Mode
  • Up to 3.2 GSPS in Dual-Channel Mode
• Noise Floor (No Signal, V_FS = 1.0 V_PP-DIFF):
  • Dual-Channel Mode: –149.5 dBFS/Hz
  • Single-Channel Mode: –152.4 dBFS/Hz
• Buffered Analog Inputs With V_CMI of 0 V:
  • Analog Input Bandwidth (–3 dB): 7 GHz
  • Usable Input Frequency Range: >10 GHz
  • Full-Scale Input Voltage (V_FS, Default): 0.8 V_PP
• Noiseless Aperture Delay (t_AD) Adjustment:
  • Precise Sampling Control: 19-fs Step Size
  • Temperature and Voltage Invariant Delays
• Easy-to-Use Synchronization Features
  • Automatic SYSREF Timing Calibration
  • Timestamp for Sample Marking
• JESD204B Subclass-1 Compliant Interface:
  • Maximum Lane Rate: 12.8 Gbps
  • Up to 16 Lanes Allows Reduced Lane Rate
• Digital Down-Converters in Dual-Channel Mode:
  • Real Output: DDC Bypass or 2x Decimation
  • Complex Output: 4x, 8x, or 16x Decimation
• Radiation Performance:
  • Total Ionizing Dose (TID): 300 krad (Si)
  • Single Event latchup (SEL): 120 MeV-cm²/mg
  • Single Event Upset (SEU) Immune Registers
• Power Consumption: 3.0 W

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