The ADC16V130 is a monolithic high performance CMOS analog-to-digital converter capable of converting analog input signals into 16-bit digital words at rates up to 130 Mega Samples Per Second (MSPS). This converter uses a differential, pipelined architecture with digital error correction and an on-chip sample-and-hold circuit to minimize power consumption and external component count while providing excellent dynamic performance. Automatic power-up calibration enables excellent dynamic performance and reduces part-to-part variation, and the ADC16V130 could be re-calibrated at any time by asserting and then de-asserting power-down. An integrated low noise and stable voltage reference and differential reference buffer amplifier easies board level design. On-chip duty cycle stabilizer with low additive jitter allows wide duty cycle range of input clock without compromising its dynamic performance. A unique sample-and-hold stage yields a full-power bandwidth of 1.4 GHz. The digital data is provided via full data rate LVDS outputs – making possible the 64-pin, 9mm x 9mm WQFN package. The ADC16V130 operates on dual power supplies +1.8V and +3.0V with a power-down feature to reduce the power consumption to very low levels while allowing fast recovery to full operation.
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Status | ACTIVE |
SubFamily | High-speed ADCs (>10MSPS) |
Resolution | 16 |
Sample Rate | 130 |
Number of input channels | 1 |
INL | |
SNR | 78.5 |
SFDR | 95.5 |
Power consumption | 755 |
Interface | Parallel LVDS |
Architecture | Pipeline |
Operating temperature range | -40 to 85 |
Rating | Catalog |
Package Group | WQFN|64 |
Package size: mm2:W x L (PKG) | [pf]64WQFN[/pf]: 81 mm2: 9 x 9 (WQFN|64) |
Approx. price | 65.60 | 1ku |
Analog input BW | 1400 |