The ADC12DL3200 is an RF-sampling, giga-sample, analog-to-digital converter (ADC) thatcan directly sample input frequencies from DC to above 10 GHz. In dual-channel mode, theADC12DL3200 can sample up to 3200 MSPS and in single-channel mode up to 6400 MSPS. Programmabletradeoffs in channel count (dual-channel mode) and Nyquist bandwidth (single-channel mode) allowdevelopment of flexible hardware that meets the needs of both high-channel count or wideinstantaneous signal bandwidth applications. Full-power input bandwidth (–3 dB) of 8.0 GHz and auseable frequency range allows direct RF sampling of L-band, S-band, C-band, and X-band forfrequency agile systems.
The ADC12DL3200 uses a low-latency, low-voltage differential signaling (LVDS) interfacefor latency sensitive applications or when the simplicity of LVDS is preferred. The interface usesup to 48 data pairs, four double data rate (DDR) clocks, and four strobe signals arranged in four12-bit data buses. The interface supports signaling rates of up to 1.6 Gbps. Strobe signalssimplify synchronization across buses and between multiple devices. The strobe is generatedinternally and can be reset at a deterministic time by the SYSREF input. Multi-devicesynchronization is further eased by innovative synchronization features such as noiseless aperturedelay (TAD) adjustment and SYSREF windowing.
Products containing the "ADC12DL3200" keyword are: ADC12DL3200ACF , ADC12DL3200EVM , ADC12DL3200EVMAll trademarks are the property of their respective owners.
Status | ACTIVE |
SubFamily | High-speed ADCs (>10MSPS) |
Resolution | 12 |
Sample Rate | 3200^6400 |
Number of input channels | 2^1 |
INL | |
SNR | 57.1 |
SFDR | 70 |
Power consumption | 3150 |
Interface | DDR LVDS^Parallel LVDS |
Architecture | Folding Interpolating |
Operating temperature range | -40 to 85 |
Rating | Catalog |
Package Group | FCBGA|256 |
Package size: mm2:W x L (PKG) | See datasheet (FCBGA) |
Approx. price | 2599.95 | 100u |
Analog input BW | 8000 |