ADC12DJ3200 - 12-bit, dual 3.2-GSPS or single 6.4-GSPS, RF-sampling analog-to-digital converter (ADC)

ADC12DJ3200 is an RF-sampling giga-sample ADC that can directly sample input frequencies from DC to above 10GHz. In dual channel mode, ADC12DJ3200 can sample up to3200-MSPS and in single channel mode up to 6400-MSPS. Programmable tradeoffs in channel count (dual channel mode) and Nyquistbandwidth (single channel mode) allow development of flexible hardware that meets the needs of bothhigh channel count or wide instantaneous signal bandwidth applications. Full power input bandwidth(-3 dB) of 8.0 GHz, with usable frequencies exceeding the -3 dB point in both dual and single channelmodes, allows direct RF sampling of L-band, S-band, C-band and X-band for frequency agilesystems.

ADC12DJ3200 uses a high speed JESD204B output interface with up to 16serialized lanes and subclass-1 compliance for deterministic latency and multi-devicesynchronization. The serial output lanes support up to 12.8 Gbps and can be configured to trade-offbit rate and number of lanes.Innovative synchronization features, including noiseless aperture delay(T_AD) adjustment and SYSREF windowing, simplify system design for phasedarray radar and MIMO communications. Optional digital downconverters (DDCs) in dual channel mode allow for reduction in interface rate (real and complexdecimation modes) and digital mixing of the signal (complex decimation modes only).

• ADC Core:
  • 12-bit Resolution
  • Up to 6.4 GSPS in single channel mode
  • Up to 3.2 GSPS in dual channel mode
• Buffered Analog Inputs with V_CMI of 0 V
  • Analog input bandwidth (-3 dB): 8.0 GHz
  • Usable input frequency range: >10 GHz
  • Full-scale input voltage (V_FS, default): 0.8 V_PP
• Noise Floor (No signal, V_FS = 1.0 V_PP):
  • Dual channel mode: -151.8 dBFS/Hz
  • Single channel mode: -154.6 dBFS/Hz
• Noiseless Aperture Delay (T_AD) Adjustment
  • Precise sampling control: 19-fs step
  • Temperature and voltage invariant delays
• Easy-to-use Synchronization Features
  • Automatic SYSREF timing calibration
  • Timestamp for sample marking
• JESD204B Serial Data Interface
  • Supports subclass 0 and 1
  • Maximum lane rate: 12.8 Gbps
  • Up to 16 lanes allows reduced lane rate
• Digital Down-Converters in Dual Channel Mode
  • Real output: DDC bypass or 2x decimation
  • Complex output: 4x, 8x or 16x decimation
  • Four independent 32-bit NCOs per DDC
• Power consumption: 3.0 W
• Power Supplies: 1.1 V, 1.9 V

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