ADC12DJ2700 - 12-Bit, Dual 2.7-GSPS or Single 5.4-GSPS, RF-Sampling Analog-to-Digital Converter (ADC)

The ADC12DJ2700 device is an RF-sampling, giga-sample, analog-to-digitalconverter (ADC) that can directly sample input frequencies from DC to above 10 GHz. In dual-channelmode, the ADC12DJ2700 can sample up to 2700 MSPS and upto 5400MSPS in single-channel mode. Programmable tradeoffs in channel count (dual-channel mode) andNyquist bandwidth (single-channel mode) allow development of flexible hardware that meets the needsof both high channel count or wide instantaneous signal bandwidth applications. Full-power inputbandwidth (–3 dB) of 8.0 GHz, with usable frequencies exceeding the –3-dB point in both dual- andsingle-channel modes, allows direct RF sampling of L-band, S-band, C-band, and X-band for frequencyagile systems.

The ADC12DJ2700 uses a high-speed JESD204B output interface with up to 16serialized lanes and subclass-1 compliance for deterministic latency and multi-devicesynchronization. The serial output lanes support up to 12.8 Gbps and can be configured to trade-offbit rate and number of lanes.Innovative synchronization features, including noiseless aperture delay(T_AD) adjustment and SYSREF windowing, simplify system design for phasedarray radar and MIMO communications. Optionaldigital down converters (DDCs) in dual-channel mode allow for reduction in interface rate (real andcomplex decimation modes) and digital mixing of the signal (complex decimation modesonly).

• ADC Core:
  • 12-Bit Resolution
  • Up to 5.4 GSPS in Single-Channel Mode
  • Up to 2.7 GSPS in Dual-Channel Mode
• Performance Specifications:
  • Noise Floor (No Signal, V_FS = 1.0 V_PP-DIFF):
    • Dual-Channel Mode: –151.6 dBFS/Hz
    • Single-Channel Mode: –153.8 dBFS/Hz
  • HD2, HD3: –65 dBc up to 3 GHz
• Buffered Analog Inputs With V_CMI of 0 V:
  • Analog Input Bandwidth (–3 dB): 8.0 GHz
  • Usable Input Frequency Range: >10 GHz
  • Full-Scale Input Voltage (V_FS, Default): 0.8 V_PP
  • Analog Input Common-Mode (V_ICM): 0 V
• Noiseless Aperture Delay (T_AD) Adjustment:
  • Precise Sampling Control: 19-fs Step
  • Simplifies Synchronization and Interleaving
  • Temperature and Voltage Invariant delays
• Easy-to-Use Synchronization Features
  • Automatic SYSREF Timing Calibration
  • Timestamp for Sample Marking
• JESD204B Serial Data Interface:
  • Supports Subclass 0 and 1
  • Maximum Lane Rate: 12.8 Gbps
  • Up to 16 Lanes Allows Reduced Lane Rate
• Digital Down-Converters in Dual-Channel Mode:
  • Real Output: DDC Bypass or 2x Decimation
  • Complex Output: 4x, 8x, or 16x Decimation
  • Four Independent 32-Bit NCOs per DDC
• Power Consumption: 2.7 W
• Power Supplies: 1.1 V, 1.9 V

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