ADC12C170 - 12-Bit, 170-MSPS, 1.1-GHz Input Bandwidth Analog-to-Digital Converter (ADC)

The ADC12C170 is a high-performance CMOS analog-to-digital converter capable of converting analog input signals into 12-Bit digital words at rates up to 170 Mega Samples Per Second (MSPS). This converter uses a differential, pipelined architecture with digital error correction and an on-chip sample-and-hold circuit to minimize power consumption and the external component count, while providing excellent dynamic performance. A unique sample-and-hold stage yields a full-power bandwidth of 1.1 GHz. The ADC12C170 operates from dual +3.3V and +1.8V power supplies and consumes 715 mW of power at 170 MSPS.

The separate +1.8V supply for the digital output interface allows lower power operation with reduced noise. A power-down feature reduces the power consumption to 5 mW while still allowing fast wake-up time to full operation. In addition there is a sleep feature which consumes 50 mW of power and has a faster wake-up time.

The differential inputs provide a full scale differential input swing equal to 2 times the reference voltage. A stable 1.0V internal voltage reference is provided, or the ADC12C170 can be operated with an external reference.

Clock mode (differential versus single-ended) and output data format (offset binary versus 2's complement) are pin-selectable. A duty cycle stabilizer maintains performance over a wide range of input clock duty cycles.

The ADC12C170 is pin compatible with the ADC14155, ADC11C125 and ADC11C170.

It is available in a 48-lead WQFN package and operates over the industrial temperature range of −40°C to +85°C.

Products containing the "ADC12C170" keyword are: ADC12C170CISQ , ADC12C170CISQ/NOPB , ADC12C170CISQ/NOPB , ADC12C170CISQNOPB , ADC12C170HFEB/NOPB , ADC12C170HFEB/NOPB , ADC12C170LFEB/NOPB

• 1.1 GHz Full Power Bandwidth
• Internal Sample-and-Hold Circuit
• Low Power Consumption
• Internal Precision 1.0V Reference
• Single-Ended or Differential Clock Modes
• Clock Duty Cycle Stabilizer
• Dual +3.3V and +1.8V Supply Operation
• Power-Down and Sleep Modes
• Offset Binary or 2's Complement Output Data Format
• Pin-Compatible: ADC14155, ADC11C125, ADC11C170
• 48-Pin WQFN Package, (7x7x0.8mm, 0.5mm Pin-Pitch)

Key Specifications

• Resolution 12 Bits
• Conversion Rate 170 MSPS
• SNR (f_IN = 70 MHz) 67.2 dBFS (typ)
• SFDR (f_IN = 70 MHz) 85.4 dBFS (typ)
• ENOB (f_IN = 70 MHz) 10.8 bits (typ)
• Full Power Bandwidth 1.1 GHz (typ)
• Power Consumption 715 mW (typ)

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