The ADC08D502 is a dual, low power, high performance CMOS analog-to-digital converter that digitizes signals to 8 bits resolution at sampling rates up to 500 MSPS. Consuming a typical 1.4 Watts at 500 MSPS from a single 1.9 Volt supply, this device is specified to have no missing codes over the full operating temperature range. The unique folding and interpolating architecture, the fully differential comparator design, the innovative design of the internal sample-and-hold amplifier and the self-calibration scheme enable a very flat response of all dynamic parameters beyond Nyquist, producing a high 7.5 ENOB with a 250 MHz input signal and a 500 MHz sample rate while providing a 10-18 B.E.R. Output formatting is offset binary and the LVDS digital outputs are compatible with IEEE 1596.3-1996, with the exception of an adjustable common mode voltage between 0.8V and 1.2V.
Each converter has a 1:2 demultiplexer that feeds two LVDS buses and reduces the output data rate on each bus to half the sampling rate.
The converter typically consumes less than 3.5 mW in the Power Down Mode and is available in a 128-lead, thermally enhanced exposed pad HLQFP and operates over the Industrial (-40°C ≤ TA ≤ +85°C) temperature range.
Products containing the "ADC08D502" keyword are: ADC08D502CIYB , ADC08D502CIYB/NOPB , ADC08D502CIYB/NOPB , ADC08D502CIYBNOPBAll trademarks are the property of their respective owners.
| Status | ACTIVE |
| SubFamily | High-speed ADCs (>10MSPS) |
| Resolution | 8 |
| Sample Rate | 500 |
| Number of input channels | 2 |
| INL | |
| SNR | 48 |
| SFDR | 55 |
| Power consumption | 1400 |
| Interface | Parallel LVDS |
| Architecture | Folding Interpolating |
| Operating temperature range | -40 to 85 |
| Rating | Catalog |
| Package Group | HLQFP|128 |
| Package size: mm2:W x L (PKG) | [pf]128HLQFP[/pf]: 484 mm2: 22 x 22 (HLQFP|128) |
| Approx. price | 59.00 | 1ku |
| Analog input BW | 1700 |