The ADC08B200 is a high speed analog-to-digital converter (ADC) with an integrated capture buffer. The 8-bit, 200 MSPS A/D core is based upon the proven ADC08200 with integrated track-and-hold and is optimized for low power consumption. This device contains a selectable size capture buffer of up to 1,024 bytes that allows fast capture of an input signal with a slower readout rate. An on-chip clock PLL circuit provides the option of on-chip clock rate multiplication to provide the high speed sampling clock.
The ADC08B200 is resistant to latch-up and the outputs are short-circuit proof. The top and bottom of the ADC08B200's reference ladder are available for connections, enabling a wide range of input possibilities. The digital outputs are TTL/CMOS compatible with a separate output power supply pin to support interfacing with 2.7V to 3.3V logic. The digital inputs and outputs are low voltage TTL/CMOS compatible and the output data format is straight binary.
The ADC08B200Q runs on an Automotive Grade Flow and is AEC-Q100 Grade 2 Qualified.
The ADC08B200 is offered in a 48-pin plastic package (TQFP) and is specified over the extended industrial temperature range of −40°C to +105°C. An evaluation board is available to assist in the easy evaluation of the ADC08B200.
Products containing the "ADC08B200" keyword are: ADC08B200CIVS , ADC08B200CIVS , ADC08B200CIVS/NOPB , ADC08B200CIVS/NOPB , ADC08B200EB , ADC08B200QCIVS NOPB , ADC08B200QCIVS/NOPB , ADC08B200QCIVS/NOPB(PLL Bypassed)
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Status | ACTIVE |
SubFamily | High-speed ADCs (>10MSPS) |
Resolution | 8 |
Sample Rate | 200 |
Number of input channels | 1 |
INL | |
SNR | 46.3 |
SFDR | 56 |
Power consumption | 543 |
Interface | Parallel CMOS |
Architecture | Pipeline |
Operating temperature range | -40 to 105 |
Rating | Catalog |
Package Group | TQFP|48 |
Package size: mm2:W x L (PKG) | [pf]48TQFP[/pf]: 81 mm2: 9 x 9 (TQFP|48) |
Approx. price | 16.50 | 1ku |
Analog input BW | 500 |