TLV320AIC3109-Q1 - Automotive Low-Power 96kHz Mono Audio Codec

Updated : 2020-01-09 14:24:11
Description

The TLV320AIC3109-Q1 device is a low-power mono audio codec with a mono headphoneamplifier and multiple input and output channels that are programmable in single-ended or fullydifferential configurations. The device includes extensive register-based power control, allowing48-kHz digital-to-analog converter (DAC) playback at as little as
14-mW consumption, making the device well-suited for low-power applications.

The record path of the TLV320AIC3109-Q1 contains integrated microphone bias, a digitallycontrolled microphone preamplifier, automatic gain control (AGC), a flexible front-end multiplexer(MUX), and a front-end analog mixer (MIX). During record, programmable filters can remove audiblenoise. The playback path includes MIX and MUX capability from the mono DAC and selected inputs,through programmable volume controls, to the various outputs.

Features

  • Qualified for Automotive Applications
  • AEC-Q100 Qualified With the Following Results:
    • Temperature Grade 2: –40°C to +105°C
    • HBM ESD Classification 2
    • CDM ESD Classification C4B
  • Mono Audio DAC:
    • 102-dBA Signal-to-Noise Ratio
    • Supports Sample Rates From 8 kHz to 96 kHz
    • 3D, Bass, Treble, EQ, or De-Emphasis Effects
  • Mono Audio ADC:
    • 92-dBA Signal-to-Noise Ratio
    • Supports Sample Rates From 8 kHz to 96 kHz
    • Digital Signal Processing and Noise Filtering
  • Four Audio Input Pins:
    • Up to Two Differential Inputs
    • Up to Two Single-Ended Inputs
  • Six Audio Output Drivers:
    • One Fully Differential or Two Single-Ended Headphone Drivers
    • Mono Pair of Fully-Differential Line Outputs
  • Low Power: 14-mW Mono, 48-kHz Playback With 3.3-V Analog Supply
  • Ultra-Low Power Mode With Passive Analog Bypass
  • Front-End Programmable Gain Amplifier (PGA)
  • Programmable Digital Gain for DAC Playback
  • Automatic Gain Control (AGC) for Record
  • Programmable Microphone Bias
  • Programmable PLL for Flexible Clock Generation
  • I2C Control Bus
  • Audio Data Formats: I2S, Left- and Right-Justified, DSP, and TDM
  • Power Supplies:
    • Analog (AVDD, DRVDD): 2.7 V to 3.6 V
    • Digital Core (DVDD): 1.525 V to 1.95 V
    • Digital I/O (IOVDD): 1.1 V to 3.6 V
  • Available in Two VQFN-32 Package Options:
    • Non-Wettable (6PAIC3109TRHBRQ1)
    • Wettable-Flank (6PAIC3109TWRHMRQ1)

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