The LMK03200 family of precision clock conditioners combine the functions of jitter cleaning/reconditioning, multiplication, and 0-delay distribution of a reference clock. The devices integrate a Voltage Controlled Oscillator (VCO), a high performance Integer-N Phase Locked Loop (PLL), a partially integrated loop filter, and up to eight outputs in various LVDS and LVPECL combinations.
The VCO output is optionally accessible on the Fout port. Internally, the VCO output goes through a VCO divider to feed the various clock distribution blocks.
Each clock distribution block includes a programmable divider, a phase synchronization circuit, a programmable delay, a clock output mux, and an LVDS or LVPECL output buffer. The PLL also features delay blocks to permit global phase adjustment of clock output phase. This allows multiple integer-related and phase-adjusted copies of the reference to be distributed to eight system components.
The clock conditioners come in a 48-pin WQFN package and are footprint compatible with other clocking devices in the same family.
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Status | ACTIVE |
SubFamily | General purpose |
Number of outputs | 9 |
Output frequency | 1296 |
Output level | LVDS^LVPECL |
Programmability | uWire |
VCC core | 3.3 |
VCC out | 3.3 |
Operating temperature range | -40 to 85 |
Package size: mm2:W x L (PKG) | [pf]48WQFN[/pf]: 49 mm2: 7 x 7 (WQFN|48) |
Approx. price | 8.50 | 1ku |
Input level | LVCMOS^LVPECL |
Features | |
Package Group | WQFN|48 |
Rating | Catalog |