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Each clock distribution block includes a programmable divider, a phase synchronization circuit, a programmable delay, a clock output mux, and an LVPECL output buffer. This allows multiple integer-related and phase-adjusted copies of the reference to be distributed to eight system components.
The clock conditioner comes in a 48-pin LLP package and is footprint compatible with other clocking devices in the same family.
Status | ACTIVE |
SubFamily | General purpose |
Number of outputs | 4 |
Output frequency | 800 |
Output level | LVPECL |
Programmability | uWire |
VCC core | 3.3 |
VCC out | 3.3 |
Operating temperature range | -40 to 85 |
Package size: mm2:W x L (PKG) | [pf]48WQFN[/pf]: 49 mm2: 7 x 7 (WQFN|48) |
Approx. price | 7.32 | 1ku |
Input level | LVCMOS^LVPECL |
Features | |
Package Group | WQFN|48 |
Rating | Catalog |