Each data selector/multiplexer contains inverters and drivers to supply full binary decoding data selection to the AND-OR gates. Separate output-control inputs are provided for each of the two 4-line sections.
The 3-state outputs can interface with and drive data lines of bus-organized systems. With all but one of the common outputs disabled (in the high-impedance state), the low impedance of the single enabled output drives the bus line to a high or low logic level. Each output has its own output-enable (OE) input. The outputs are disabled when their respective OE is high.
Status | ACTIVE |
SubFamily | Encoders & decoders |
Technology Family | HC |
VCC | 6 |
Bits | 4 |
Voltage | 3.3^5 |
F @ nom voltage | 28 |
ICC @ nom voltage | 0.08 |
tpd @ Nom Voltage | 38 |
Rating | Automotive |
Operating temperature range | -40 to 125 |
Package Group | SOIC|16 |
Package size: mm2:W x L (PKG) | [pf]16SOIC[/pf]: 59 mm2: 6 x 9.9 (SOIC|16) |
Approx. price | 0.16 | 1ku |