This dual positive-edge-triggered D-type flip-flop is designed for 1.65-V to 5.5-V VCC operation.
When data at the data (D) input meets the setup time requirement, the data is transferred to the Q output on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval, data at the D input can be changed without affecting the levels at the outputs.
NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the package.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.
Products containing the "SN74LVC2G79" keyword are: SN74LVC2G79DCTR , SN74LVC2G79DCTR , SN74LVC2G79DCTRE6 , SN74LVC2G79DCUR , SN74LVC2G79DCUR , SN74LVC2G79DCURE4 , SN74LVC2G79DCURE4 , SN74LVC2G79DCURG4 , SN74LVC2G79DCURG4 , SN74LVC2G79YEPR , SN74LVC2G79YZPR , SN74LVC2G79YZPRStatus | ACTIVE |
SubFamily | D-type flip-flop |
Technology Family | LVC |
VCC | 5.5 |
Bits | 2 |
Voltage | 1.8^2.5^3.3^5 |
F @ nom voltage | 150 |
ICC @ nom voltage | 0.005 |
tpd @ Nom Voltage | 9.9^7^5.2^4.5 |
3-state output | No |
Rating | Catalog |
Operating temperature range | -40 to 125 |
Package Group | DSBGA|8 |
Package size: mm2:W x L (PKG) | See datasheet (DSBGA) |
Approx. price | 0.14 | 1ku |