This single positive-edge-triggered D-type flip-flop is operational at 0.8-V to 2.7-V VCC, but is designed specifically for 1.65-V to 1.95-V VCC operation.
When data at the data (D) input meets the setup time requirement, the data is transferred to the Q output on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval, data at the D input can be changed without affecting the levels at the outputs.
NanoFree package technology is a major breakthrough in IC packaging concepts, using the die as the package.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.
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Status | ACTIVE |
SubFamily | D-type flip-flop |
Technology Family | AUC |
VCC | 2.7 |
Bits | 2 |
Voltage | 0.8^1.2^1.5^1.8^2.5 |
F @ nom voltage | 250 |
ICC @ nom voltage | 0.01 |
tpd @ Nom Voltage | 5^3.9^2.5^1.9^1.3 |
3-state output | No |
Rating | Catalog |
Operating temperature range | -40 to 85 |
Package Group | DSBGA|8 |
Package size: mm2:W x L (PKG) | See datasheet (DSBGA) |
Approx. price | 0.14 | 1ku |